Marvell Alaska 88E1111 Ultra Gigabit Ethernet Transceiver Datasheet

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"Marvell Alaska 88E1111是一款集成的10/100/1000 Ultra Gigabit Ethernet收发器的数据手册。文档编号MV-S100649-00，修订版M，发布日期为2020年8月31日，公开分类。" 本文档详细介绍的是Marvell公司的Alaska系列中的88E1111集成千兆以太网收发器。该器件旨在提供高速的网络连接能力，支持10Mbps、100Mbps以及1000Mbps的传输速率，属于超千兆以太网技术范畴。收发器是网络硬件中的关键组件，它负责将数据转换成可以在物理介质上传输的信号，并能接收并解码这些信号，从而实现设备间的通信。文档中可能涵盖了以下关键知识点： 1. **产品概述**：88E1111收发器的设计特性，包括其高性能、低功耗和高集成度，使其适合于各种网络应用，如企业级交换机、路由器和服务器接口等。 2. **功能特性**：收发器的特性列表，可能包括支持多种网络速度、自动协商功能（Auto-Negotiation）、流量控制（Flow Control）、节能以太网（EEE）支持，以及错误检测和校正机制等。 3. **电气和物理接口**：详细说明了88E1111与物理介质的连接方式，如MII（Media Independent Interface）、GMII（Gigabit Media Independent Interface）或RGMII（Reduced GMII）等。 4. **性能指标**：可能包括数据传输速率、功耗、电压需求、工作温度范围以及电磁兼容性（EMC）标准等。 5. **物理层规范**：遵循的IEEE 802.3以太网标准和其他相关协议，例如802.3ab（1000BASE-T）。 6. **应用示例**：提供使用88E1111收发器设计网络设备的实例，帮助开发者理解如何在实际产品中集成和利用该器件。 7. **封装和引脚定义**：描述了收发器的物理封装形式和各引脚的功能，这对于硬件设计人员来说至关重要。 8. **警告与免责声明**：Marvell公司明确声明，文档提供的所有信息"按原样"提供，不提供任何明示或暗示的保证，包括但不限于适销性、特定用途适用性和非侵权性的保证。 9. **知识产权**：强调文档及其可能包含的软件或固件的所有权归Marvell或其许可方所有，并受知识产权法律保护。未经许可，不得用于任何Marvell知识产权。 10. **使用限制**：提醒用户，Marvell产品不得用于关键应用，如医疗、航空、军事等领域，因为这些领域的设备通常要求更高的安全性和可靠性标准。此数据手册提供了全面的技术规格和设计指导，帮助工程师理解和使用88E1111收发器进行网络设备的开发和制造。

Page 16 Document Classification: Public August 31, 2020

Alaska 88E1111

Datasheet

Figure 37: PMOS Output Impedance (2.5V) Trend Line..................................................................................108

Figure 38: NMOS Output Impedance (2.5V) Trend Line .................................................................................108

Figure 39: Signal Reflections, using the 50 ohm Setting, 60 ohm line.............................................................109

Figure 40: Clean signal after manual calibration for the 60 ohm .....................................................................109

Figure 41: Single LED Connection...................................................................................................................111

Figure 42: Bi-Color LED Connection................................................................................................................111

3 Register Description.......................................................................................................................121

Figure 43: Register Map Summary .................................................................................................................122

4 Electrical Specifications ................................................................................................................ 183

Figure 44: CML I/Os.........................................................................................................................................197

Figure 45: AC connections (CML or LVDS receiver) or DC connection LVDS receiver ..................................199

Figure 46: DC connection to a CML receiver ...................................................................................................200

Figure 47: Input Differential Hysteresis............................................................................................................201

Figure 48: Reset Timing...................................................................................................................................203

Figure 49: XTAL1 Input Clock Timing ..............................................................................................................204

Figure 50: 125CLK Output Timing ...................................................................................................................205

Figure 51: GMII Transmit Timing .....................................................................................................................206

Figure 52: GMII Receive Timing ......................................................................................................................207

Figure 53: 10/100 Mbps Transmit Timing ........................................................................................................208

Figure 54: 10/100 Mbps Receive Timing .........................................................................................................209

Figure 55: TBI Transmit Timing .......................................................................................................................210

Figure 56: TBI Receive Timing ........................................................................................................................211

Figure 57: RGMII/RTBI Multiplexing and Timing .............................................................................................212

Figure 58: GTX_CLK Delay Timing - Register 20.1 = 0...................................................................................213

Figure 59: GTX_CLK Delay Timing - Register 20.1 = 1 (add delay)................................................................213

Figure 60: RGMII RX_CLK Delay Timing - Register 20.7 = 0..........................................................................214

Figure 61: RGMII RX_CLK Delay Timing - Register 20.7 = 1 (add delay).......................................................214

Figure 62: Serial Interface Rise and Fall Times...............................................................................................215

Figure 63: GMII/MII to 10/100/1000BASE-T Transmit Latency Timing............................................................217

Figure 64: 10/100/1000BASE-T to GMII/MII Receive Latency Timing.............................................................219

Figure 65: GMII to 1000BASE-X Transmit Latency Timing .............................................................................220

Figure 66: 1000BASE-X to GMII Receive Latency Timing ..............................................................................221

Figure 67: RGMII/MII to 10/100/1000BASE-T Transmit Latency Timing .........................................................222

Figure 68: 10/100/1000BASE-T to RGMII Receive Latency Timing ................................................................223

Figure 69: RGMII to 1000BASE-X Transmit Latency Timing ..........................................................................

.224

Figure 70: 1000BASE-X to RGMII Receive Latency Timing............................................................................225

Figure 71: TBI to 100BASE-T Transmit Latency Timing..................................................................................226

Figure 72: 1000BASE-T to TBI Receive Latency Timing .................................................................................227

Figure 73: RTBI to 1000BASE-T Transmit Latency Timing .............................................................................228

Figure 74: 1000BASE-T to RTBI Receive Latency Timing ..............................................................................228

Figure 75: SGMII to 10/100/1000BASE-T Transmit Latency Timing ...............................................................229

Figure 76: 10/100/1000BASE-T to SGMII Receive Latency Timing ................................................................230

August 31, 2020 Document Classification: Public Page 17

Figure 77: 1000BASE-X to 1000BASE-T Transmit Latency Timing ................................................................231

Figure 78: 1000BASE-T to 1000BASE-X Receive Latency Timing .................................................................232

Figure 79: Serial Management Interface Timing ..............................................................................................233

Figure 80: Two-Wire Serial Interface Timing ...................................................................................................235

Figure 81: JTAG Timing...................................................................................................................................236

5 Package Mechanical Dimensions .................................................................................................238

Figure 82: 117-pin TFBGA Package Mechanical Drawings.............................................................................238

Figure 83: 128-pin PQFP Package Mechanical Drawings...............................................................................240

Figure 84: 96-pin aQFN Package Mechanical Drawings - Top View...............................................................241

Figure 85: 96-pin aQFN Package Mechanical Drawings - Bottom View..........................................................242

Figure 86: 96-pin BCC Package - Top View - OBSOLETE - No Longer Available - Replaced by the

96-Pin aQFN Package....................................................................................................................245

Figure 87: 96-pin BCC Package - Bottom View - OBSOLETE - No Longer Available - Replaced by

the 96-Pin aQFN Package..............................................................................................................246

6 Part Order Numbering/Package Marking......................................................................................247

Figure 88: Sample Part Number ......................................................................................................................247

Figure 89: 88E1111 117-pin TFBGA Commercial RoHS 6/6 Compliant Package Marking and Pin 1

Location ..........................................................................................................................................248

Figure 90: 88E1111 117-pin TFBGA Commercial Green Compliant Package Marking and Pin 1

Location ..........................................................................................................................................249

Figure 91: 88E1111 128-pin PQFP Commercial RoHS 6/6 Compliant Package Marking and Pin 1

Location ..........................................................................................................................................249

Figure 92: 88E1111 96-pin aQFN Commercial Green Compliant Package Marking and Pin 1 Location ........250

Figure 93: 88E1111 117-pin TFBGA Industrial RoHS 6/6 Compliant Package Marking and Pin 1

Location ..........................................................................................................................................250

Figure 94: 88E1111 117-pin TFBGA Industrial Green Compliant Package Marking and Pin 1 Location ........251

Figure 95: 88E1111 96-pin aQFN Industrial Green Compliant Package Marking and Pin 1 Location.............251

A Revision History .............................................................................................................................252