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S3C6410 RISC Microprocessor User's Manual
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"三星6410用户手册,包含了对S3C6410X RISC微处理器的详细说明,由三星电子于2008年8月22日发布,版本1.10。手册是三星的机密财产,版权归三星电子所有。手册警告用户可能存在错误或遗漏,并指出三星不承担由此产生的任何后果,同时三星有权随时对产品进行改进而不事先通知。此外,购买半导体设备并不意味着获得三星或其他公司的专利权许可。三星不对产品的适用性、特定用途的性能或使用任何产品或电路可能产生的责任提供任何保修、陈述或保证。"
S3C6410是一款基于RISC(Reduced Instruction Set Computer)架构的微处理器,由三星电子设计制造。RISC架构以其高效的指令集和精简的硬件结构著称,通常在嵌入式系统中应用广泛。S3C6410X可能是S3C6410的一个特定变种或升级版,可能包含了额外的功能或优化。
手册的核心内容可能包括以下几点:
1. **处理器架构**:详述S3C6410的CPU内核设计,如其指令集、流水线结构、缓存系统以及多线程支持等特性。
2. **外设接口**:介绍处理器支持的各种外部设备接口,如USB、Ethernet、UART、GPIO、LCD控制器、摄像头接口等,这些接口对于嵌入式系统中的硬件集成至关重要。
3. **内存管理**:解释内存控制器的工作方式,包括RAM和ROM的配置、内存映射以及虚拟内存管理。
4. **电源管理**:描述S3C6410的低功耗特性,如动态电压频率调整(DVFS)、睡眠模式和唤醒机制等,这些对于电池供电的设备非常重要。
5. **开发环境与工具**:可能包括如何设置开发环境,使用调试器、编译器和其他开发工具的信息。
6. **硬件设计指南**:为系统级设计者提供如何连接处理器与其他组件的指导,如电源设计、时钟系统和散热方案。
7. **固件和驱动程序**:说明如何编写和配置固件以及设备驱动程序,以便使处理器与各种硬件设备协同工作。
8. **错误处理和异常**:详述处理器的错误检测和恢复机制,以及如何处理中断和异常。
9. **安全性和认证**:可能涉及处理器的安全特性,如加密引擎、安全区域以及通过各种行业标准认证的要求。
10. **案例研究和应用示例**:可能包含一些实际应用的例子,帮助开发者理解如何在不同场景下使用S3C6410。
由于手册的版本为1.10,可能还包含了关于三星对产品进行改进和更新的信息,这些改进可能涉及到性能提升、能效优化或者新功能的添加。
三星6410用户手册是开发基于该处理器的嵌入式系统的关键参考资料,涵盖了从硬件设计到软件开发的全方位信息,对工程师来说是必不可少的工具。
xvi S3C6410X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 14 Display Controller
14.4.5 Palette usage .................................................................................................................................14-16
14.4.5.1 Palette Configuration and Format Control..............................................................................14-16
14.4.6 Window Blending ...........................................................................................................................14-18
14.4.6.1 Overview.................................................................................................................................14-18
14.4.6.2 Blending Diagram/Details ...........................................................................................................14-20
14.4.7 COLOR-KEY Function...................................................................................................................14-22
14.4.8 VTIME CONTROLLER OPERATION ............................................................................................14-25
14.4.8.1 RGB Interface.........................................................................................................................14-25
14.4.8.2 I80 Interface Controller..........................................................................................................14-26
14.4.9 LDI Command Control ...................................................................................................................14-27
14.4.9.1 Auto Command.......................................................................................................................14-27
14.4.9.2 Normal Command ..................................................................................................................14-27
14.4.10 I80 CPU Interface Trigger............................................................................................................14-29
14.4.11 Interrupt........................................................................................................................................14-29
14.4.12 Virtual Display ..............................................................................................................................14-29
14.4.13 RGB Interface IO .........................................................................................................................14-31
14.4.14 LCD I80 INTERFACE IO..............................................................................................................14-32
14.4.14 ITU-R BT.601 INTERFACE IO.....................................................................................................14-33
14.4.15 LCD DaTA PiN MAP....................................................................................................................14-34
14.4.16 LCD NORMAL/BY-PASS MODE SELECTION ...........................................................................14-36
14.5 Programmer’s Model.............................................................................................................................14-37
14.5.1 Overview ........................................................................................................................................14-37
14.5.2 SFR Memory Map..........................................................................................................................14-37
14.6 Individual Register Descriptions............................................................................................................14-40
14.6.1 Video Main Control 0 Register.......................................................................................................14-40
14.6.2 Video Main Control 1 Register.......................................................................................................14-42
14.6.3 Video Main Control 2 Register.......................................................................................................14-43
14.6.4 VIDEO Time Control 0 Register.....................................................................................................14-43
14.6.5 Video Time Control 1 Register.......................................................................................................14-44
14.6.6 VIDEO Time Control 2 Register.....................................................................................................14-44
14.6.7 Window 0 Control Register ............................................................................................................14-44
14.6.8 Window 1 Control Register ...........................................................................................................14-46
14.6.9 Window 2 Control Register ............................................................................................................14-48
14.6.10 Window 3 Control Register ..........................................................................................................14-50
14.6.11 Window 4 Control Register ..........................................................................................................14-51
14.6.12 Window 0 Position Control A Register.........................................................................................14-52
14.6.13 Window 0 Position Control B Register.........................................................................................14-52
14.6.14 Window 0 Position Control C Register.........................................................................................14-52
14.6.15 Window 1 Position Control A Register.........................................................................................14-53
14.6.16 Window 1 Position Control B Register.........................................................................................14-53
14.6.17 Window 1 Position Control C Register..................................................................................
......14-54
14.6.18 Window 1 Position Control D Register.........................................................................................14-54
14.6.19 Window 2 Position Control A Register.........................................................................................14-54
S3C6410X_USER’S MANUAL_REV 1.10 xvii
Table of Contents (Continued)
Chapter 14 Display Controller
14.6.20 Window 2 Position Control B Register ........................................................................................14-55
14.6.21 Window 2 Position Control C Register ........................................................................................14-55
14.6.22 Window 2 Position Control D Register ........................................................................................14-55
14.6.23 Window 3 Position Control A Register ........................................................................................14-56
14.6.24 Window 3 Position Control B Register ........................................................................................14-56
14.6.25 Window 3 Position Control C Register ........................................................................................14-57
14.6.26 Window 4 Position Control a Register.........................................................................................14-57
14.6.27 Window 4 Position Control B Register ........................................................................................14-58
14.6.28 Window 4 Position Control C Register ........................................................................................14-58
14.6.29 FRAME Buffer Address 0 Register..............................................................................................14-59
14.6.30 FRAME Buffer Address 1 Register..............................................................................................14-59
14.6.31 FRAME Buffer Address 2 Register..............................................................................................14-60
14.6.32 VIDEO interrupt Control 0 Register .............................................................................................14-60
14.6.33 VIDEO interrupt Control 1 Register .............................................................................................14-61
14.6.34 Win1 Color Key 0 Register ..........................................................................................................14-62
14.6.35 WIN 1 Color key 1 Register.........................................................................................................14-62
14.6.36 Win2 Color Key 0 Register ..........................................................................................................14-63
14.6.37 WIN2 Color key 1 Register..........................................................................................................14-63
14.6.38 Win3 Color Key 0 Register ..............................................................................................
............14-64
14.6.39 WIN3 Color key 1 Register..........................................................................................................14-64
14.6.40 Win4 Color Key 0 Register ..........................................................................................................14-65
14.6.41 WIN4 Color key 1 Register..........................................................................................................14-66
14.6.42 Dithering Control 1 Register ........................................................................................................14-67
14.6.43 WIN0 Color MAP .........................................................................................................................14-67
14.6.44 WIN1 Color MAP .........................................................................................................................14-68
14.6.44 WIN1 Color MAP .........................................................................................................................14-68
14.6.45 WIN2 Color MAP .........................................................................................................................14-68
14.6.46 WIN3 Color MAP .........................................................................................................................14-68
14.6.47 WIN4 Color MAP .........................................................................................................................14-69
14.6.48 Window Palette control Register .................................................................................................14-69
14.6.49 I80 / RGB Trigger Control Register .............................................................................................14-70
14.6.50 ITU 601 Interface control 0..........................................................................................................14-70
14.6.51 LCD I80 Interface Control 0.........................................................................................................14-71
14.6.52 LCD I80 Interface Control 1.........................................................................................................14-72
14.6.53 LCD I80 Interface Command Control 0.......................................................................................14-72
14.6.54 LCD I80 Interface Command Control 1.......................................................................................14-74
14.6.55 I80 System Interface Manual Command Control 0 .....................................................................14-74
14.6.56 I80 System Interface Manual Command Control 1 .....................................................................14-75
14.6.57 I80 System Interface Manual Command Control 2 .....................................................................14-75
14.6.58 LCD I80 Interface Command.......................................................................................................14-76
14.6.59 Window 2’s Palette Data .............................................................................................................14-76
14.6.60 Window 3’s Palette Data .............................................................................................................14-77
14.6.61 Window 4’s Palette Data .............................................................................................................14-77
14.6.62 WIN0 Palette Ram Access Address (not SFR) ...........................................................................14-77
14.6.63 WIN1 Palette Ram Access Address (not SFR) ...........................................................................14-78
xviii S3C6410X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 15 Post Processor
15.1 Overview................................................................................................................................................15-1
15.2 Features ................................................................................................................................................15-2
15.3 A Source and Destination Image Data Format .....................................................................................15-3
15.3.1 DMA Mode Operation ....................................................................................................................15-4
15.3.2 FIFO Mode Operation....................................................................................................................15-7
15.4 Image Size and Scale Ratio..................................................................................................................15-7
15.5 DMA operation of Source and Destination Image.................................................................................15-9
15.5.1 Start address..................................................................................................................................15-10
15.5.2 End address...................................................................................................................................15-10
15.6 Frame Management of POST Processor..............................................................................................15-12
15.6.1 Per Frame Management Mode......................................................................................................15-12
15.6.2 Free Run Mode ..............................................................................................................................15-12
15.7 Register File Lists..................................................................................................................................15-13
15.7.1 MODE Control Register .................................................................................................................15-15
15.7.3 Pre-Scale Image Size Register......................................................................................................15-17
15.7.4 Source Image Size Register ..........................................................................................................15-18
15.7.5 Horizontal Main Scale Ratio Register ............................................................................................15-18
15.7.6 Vertical Main Scale Ratio Register ................................................................................................15-18
15.7.7 Destination Image Size Register ...................................................................................................15-19
15.7.8 Pre-Scale Shift Factor Register .....................................................................................................15-19
15.7.9 DMA Start Address Register..............................................................................................
............20
15.7.10 DMA End Address Register.........................................................................................................15-21
15.7.11 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register .............................................15-22
15.7.12 Next Frame DMA Start Address Register....................................................................................15-23
15.7.13 Next Frame DMA End Address Register.....................................................................................15-24
15.7.14 DMA Start address Register for Output Cb and Cr .....................................................................15-24
15.7.15 DMA End Address Register for Output Cb and Cr ......................................................................15-25
15.7.16 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr ..........15-25
15.7.17 15.26 Next Frame DMA Start Address Register for Output Cb and Cr.......................................15-25
15.7.18 Next Frame DMA End Address Register for Output Cb and Cr ..................................................15-26
15.7.19 POSTENVID Register to Enable Video Processing ....................................................................15-26
15.7.20 MODE Control Register 2 ............................................................................................................15-27
S3C6410X_USER’S MANUAL_REV 1.10 xix
Table of Contents (Continued)
Chapter 16 TV Scaler
16.1 Overview ...............................................................................................................................................16-1
16.2 Features................................................................................................................................................16-2
16.3 A Source and Destination Image Data Format.....................................................................................16-3
16.3.1 DMA Mode Operation....................................................................................................................16-4
16.3.2 FIFO Mode Operation....................................................................................................................16-7
16.4 Image Size and Scale Ratio..................................................................................................................16-7
16.5 DMA operation of Source and Destination Image ................................................................................16-9
16.5.1 Start address .................................................................................................................................16-10
16.5.2 End address...................................................................................................................................16-10
16.6 Frame Management of TV Scaler.........................................................................................................16-12
16.6.1 Per Frame Management Mode......................................................................................................16-12
16.6.2 Free Run Mode..............................................................................................................................16-12
16.7 Register File Lists .................................................................................................................................16-13
16.7.1 MODE Control Register.................................................................................................................16-15
16.7.3 Pre-Scale Image Size Register .....................................................................................................16-17
16.7.4 Source Image Size Register..........................................................................................................16-18
16.7.5 Horizontal Main Scale Ratio Register............................................................................................16-18
16.7.6 Vertical Main Scale Ratio Register................................................................................................16-18
16.7.7 Destination Image Size Register ...................................................................................................16-19
16.7.8 Pre-Scale Shift Factor Register.....................................................................................................16-19
16.7.9 DMA Start Address Register .........................................................................................................16-20
16.7.10 DMA End Address Register.........................................................................................................16-20
16.7.11 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register...........................................16-21
16.7.12 Next Frame DMA Start Address Register ...................................................................................16-21
16.7.13 Next Frame DMA End Address Register.....................................................................................16-22
16.7.14 DMA Start Address Register for Output Cb and Cr.....................................................................16-22
16.7.15 DMA End Address Register for Output Cb and Cr......................................................................16-23
16.7.16 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register for Output Cb and Cr ........16-23
16.7.17 Next Frame DMA Start Address Register for Output Cb and Cr.................................................16-23
16.7.18 Next Frame DMA End Address Register for Output Cb and Cr..................................................16-24
16.7.19 POSTENVID Register for Enable Video Processing...................................................................16-24
16.7.20 MODE Control Register 2............................................................................................................16-25
xx S3C6410X_USER’S MANUAL_REV 1.00
Table of Contents (Continued)
Chapter 17 TV Encoder
17.1 Overview................................................................................................................................................17-1
17.2 Feature ..................................................................................................................................................17-1
17.3 Block Diagram .......................................................................................................................................17-2
17.4 Functional Descriptions.........................................................................................................................17-3
17.4.1 Composition Of Analog Composite Signal.....................................................................................17-4
17.4.2 Common Ntsc System ...................................................................................................................17-5
17.4.3 Common Pal System .....................................................................................................................17-6
17.4.4 Composition Of Screen..................................................................................................................17-7
17.4.5 Requested Horizontal Timing ........................................................................................................17-8
17.4.6 Requested Vertical Timing.............................................................................................................17-9
17.4.7 Macrovision (Anti Taping) ..............................................................................................................17-10
17.5 Dac Board Configure Guide ..................................................................................................................17-11
17.6 Tv Encoder Register Summary .............................................................................................................17-12
17.7 Individual Register Descriptions............................................................................................................17-13
17.7.1 TVENCREG1 .................................................................................................................................17-13
17.7.2 TVENCREG2 .................................................................................................................................17-14
17.7.3 TVENCREG3 .................................................................................................................................17-14
17.7.4 TVENCREG4 .................................................................................................................................17-14
17.7.5 TVENCREG5 .................................................................................................................................17-15
17.7.6 TVENCREG6 .................................................................................................................................17-15
17.7.7 TVENCREG7 .................................................................................................................................17-15
17.7.8 TVENCREG8 ...............................................................................................................
..................17-16
17.7.9 TVENCREG9 .................................................................................................................................17-16
17.7.10 TVENCREG10 .............................................................................................................................17-17
17.7.11 TVENCREG11 .............................................................................................................................17-17
17.7.12 TVENCREG12 .............................................................................................................................17-17
17.7.13 TVENCREG14 .............................................................................................................................17-18
17.7.14 TVENCREG15 .............................................................................................................................17-18
17.7.15 TVENCREG18 .............................................................................................................................17-20
17.7.16 TVENCREG19 .............................................................................................................................17-20
17.7.17 TVENCREG20 .............................................................................................................................17-21
17.7.18 TVENCREG21 .............................................................................................................................17-22
17.7.19 TVENCREG23 .............................................................................................................................17-22
17.7.20 TVENCREG25 .............................................................................................................................17-23
17.7.21 TVENCREG26 .............................................................................................................................17-24
17.7.22 TVENCREG27 .............................................................................................................................17-24
17.7.23 TVENCREG28 .............................................................................................................................17-25
17.7.24 TVENCREG29 .............................................................................................................................17-25
17.7.25 TVENCREG30 .............................................................................................................................17-25
17.7.26 TVENCREG31 .............................................................................................................................17-26
17.7.27 TVENCREG32 .............................................................................................................................17-26
17.7.28 TVENCREG33 .............................................................................................................................17-26
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