I2C总线协议详解及入门指南

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"I2C总线协议官方文档，适合初学者，内容涵盖I2C总线的不同模式和速率，由Philips Semiconductors（现为NXPSemiconductors）开发，是一种高效的双向两线制总线协议，用于集成电路间的通信。" I2C总线协议是Philips Semiconductors（现在是NXPSemiconductors）设计的一种高效、双向的两线通信协议，其主要特点是只需要两条线：串行数据线(SDA)和串行时钟线(SCL)。这种协议使得不同设备间的数据传输变得简单且节省资源，尤其适用于嵌入式系统和微控制器应用。 I2C总线有多种工作模式，以适应不同的速度需求： 1. **标准模式(Standard-mode)**: 在标准模式下，数据传输速率可达100kbit/s。这是最早的I2C模式，适合对速度要求不高的应用场景。 2. **快速模式(Fast-mode)**: 提升了传输速率，达到400kbit/s，适用于需要更快通信速度的场合。 3. **快速模式Plus(Fast-mode Plus, Fm+)**: 进一步提高传输速率，达到1Mbit/s，适合更高性能的设备之间的通信。 4. **高速模式(High-Speed mode)**: 数据传输速率提升至3.4Mbit/s，满足高速数据交换的需求。 5. **超快速模式(UltraFast-mode)**: 这是一种单向传输模式，数据传输速率高达5Mbit/s，主要用于需要极快响应时间的应用。 I2C协议规定了主设备和从设备的概念。主设备通常是一个微控制器或处理器，它控制时钟信号并启动和停止数据传输。从设备是响应主设备请求并提供或接收数据的设备。每个设备都有一个唯一的7位或10位地址，以便主设备可以寻址特定的从设备。协议还定义了开始和停止条件，以及应答和非应答信号。在数据传输过程中，每次数据传输后，从设备都会通过拉低SDA线来发送一个应答位，表明已成功接收或发送数据。如果主设备没有收到应答，会重新发送数据或者发起停止条件。此外，I2C总线还支持多主控环境，这意味着在同一个总线上可以有多个设备同时作为主设备，但只有一个主设备可以控制总线进行通信。为了防止冲突，主设备之间需要通过仲裁机制来决定谁拥有总线使用权。 I2C总线协议因其简洁、高效和广泛兼容性，成为了现代电子设计中不可或缺的一部分，尤其在嵌入式系统和物联网(IoT)设备中得到了广泛应用。对于初学者来说，理解其基本原理和操作模式是进入这个领域的关键步骤。通过阅读官方文档，可以深入了解I2C的工作细节，包括如何设置时钟、处理错误、实现总线扩展等。

User manual Rev. 6 — 4 April 2014 11 of 64

NXP Semiconductors

UM10204

C-bus specification and user manual

3.1.7 Clock synchronization

Two masters can begin transmitting on a free bus at the same time and there must be a

method for deciding which takes control of the bus and complete its transmission. This is

done by clock synchronization and arbitration. In single master systems, clock

synchronization and arbitration are not needed.

Clock synchronization is performed using the wired-AND connection of I

C interfaces to

the SCL line. This means that a HIGH to LOW transition on the SCL line causes the

masters concerned to start counting off their LOW period and, once a master clock has

gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see

Figure 7

). However, if another clock is still within its LOW period, the LOW to HIGH

transition of this clock may not change the state of the SCL line. The SCL line is therefore

held LOW by the master with the longest LOW period. Masters with shorter LOW periods

enter a HIGH wait-state during this time.

When all masters concerned have counted off their LOW period, the clock line is released

and goes HIGH. There is then no difference between the master clocks and the state of

the SCL line, and all the masters start counting their HIGH periods. The first master to

complete its HIGH period pulls the SCL line LOW again.

In this way, a synchronized SCL clock is generated with its LOW period determined by the

master with the longest clock LOW period, and its HIGH period determined by the one

with the shortest clock HIGH period.

3.1.8 Arbitration

Arbitration, like synchronization, refers to a portion of the protocol required only if more

than one master is used in the system. Slaves are not involved in the arbitration

procedure. A master may start a transfer only if the bus is free. Two masters may

generate a START condition within the minimum hold time (t

HD;STA

) of the START

condition which results in a valid START condition on the bus. Arbitration is then required

to determine which master will complete its transmission.

Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks to

see if the SDA level matches what it has sent. This process may take many bits. Two

masters can actually complete an entire transaction without error, as long as the

Fig 7. Clock synchronization during the arbitration procedure

CLK

SCL

counter

reset

wait

state

start counting

HIGH period

mbc632

User manual Rev. 6 — 4 April 2014 12 of 64

NXP Semiconductors

UM10204

C-bus specification and user manual

transmissions are identical. The first time a master tries to send a HIGH, but detects that

the SDA level is LOW, the master knows that it has lost the arbitration and turns off its

SDA output driver. The other master goes on to complete its transaction.

No information is lost during the arbitration process. A master that loses the arbitration

can generate clock pulses until the end of the byte in which it loses the arbitration and

must restart its transaction when the bus is free.

If a master also incorporates a slave function and it loses arbitration during the addressing

stage, it is possible that the winning master is trying to address it. The losing master must

therefore switch over immediately to its slave mode.

Figure 8

shows the arbitration procedure for two masters. More may be involved

depending on how many masters are connected to the bus. The moment there is a

difference between the internal data level of the master generating DATA1 and the actual

level on the SDA line, the DATA1 output is switched off. This does not affect the data

transfer initiated by the winning master.

Since control of the I

C-bus is decided solely on the address and data sent by competing

masters, there is no central master, nor any order of priority on the bus.

There is an undefined condition if the arbitration procedure is still in progress at the

moment when one master sends a repeated START or a STOP condition while the other

master is still sending data. In other words, the following combinations result in an

undefined condition:

• Master 1 sends a repeated START condition and master 2 sends a data bit.

• Master 1 sends a STOP condition and master 2 sends a data bit.

• Master 1 sends a repeated START condition and master 2 sends a STOP condition.

Fig 8. Arbitration procedure of two masters

msc609

DATA

SDA

SCL

master 1 loses arbitration

DATA 1 SDA

User manual Rev. 6 — 4 April 2014 13 of 64

NXP Semiconductors

UM10204

C-bus specification and user manual

3.1.9 Clock stretching

Clock stretching pauses a transaction by holding the SCL line LOW. The transaction

cannot continue until the line is released HIGH again. Clock stretching is optional and in

fact, most slave devices do not include an SCL driver so they are unable to stretch the

clock.

On the byte level, a device may be able to receive bytes of data at a fast rate, but needs

more time to store a received byte or prepare another byte to be transmitted. Slaves can

then hold the SCL line LOW after reception and acknowledgment of a byte to force the

master into a wait state until the slave is ready for the next byte transfer in a type of

handshake procedure (see Figure 7

On the bit level, a device such as a microcontroller with or without limited hardware for the

C-bus, can slow down the bus clock by extending each clock LOW period. The speed of

any master is adapted to the internal operating rate of this device.

In Hs-mode, this handshake feature can only be used on byte level (see Section 5.3.2

3.1.10 The slave address and R/W bit

Data transfers follow the format shown in Figure 9. After the START condition (S), a slave

address is sent. This address is seven bits long followed by an eighth bit which is a data

direction bit (R/W

) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a

request for data (READ) (refer to Figure 10

). A data transfer is always terminated by a

STOP condition (P) generated by the master. However, if a master still wishes to

communicate on the bus, it can generate a repeated START condition (Sr) and address

another slave without first generating a STOP condition. Various combinations of

read/write formats are then possible within such a transfer.

Fig 9. A complete data transfer

1 - 7 8 9 1 - 7 8 9 1 - 7 8 9

STOP

condition

START

condition

DATA ACKDATA ACKADDRESS ACKR/W

SDA

SCL

mbc604

Fig 10. The first byte after the START procedure

mbc608

R/W

LSBMSB

slave address

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