华邦W25Q128FV：高性能128M-bit串行闪存

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"华邦W25Q128FV是一款128M位的串行闪存存储器，适用于空间有限、引脚和电源受限的系统。25Q系列提供了一般串行闪存设备无法比拟的灵活性和性能。它们非常适合用于RAM的代码影射、直接从双/四SPI（XIP）执行代码以及存储语音、文本和数据。该设备在2.7V至3.6V的单电源供电下工作，活动电流低至4mA，待机功耗仅为1µA。产品提供节省空间的封装选项。" 华邦W25Q128FV是一款高性能的串行闪存，它提供了128M位（即16MB）的数据存储容量，特别适合于那些对空间、引脚数量和功耗有严格要求的应用。其关键特性包括： 1. **多模式SPI接口**: 华邦W25Q128FV支持标准SPI、双SPI、四SPI和快速四输入（QPI）操作模式，这些模式提供了更高的数据传输速率，使系统能够更快地读取和写入数据。 2. **低功耗设计**: 设备在工作时仅消耗4mA电流，而在待机状态下，功耗降低至1µA，这对于电池供电或能源敏感的应用来说是理想的选择。 3. **执行指令功能**: 除了基本的读写操作外，还支持直接在SPI总线上执行代码（XIP，Execute-In-Place），使得程序可以直接从闪存运行，无需先加载到RAM，减少了系统资源的占用。 4. **封装形式多样**: 提供了SOIC/VSOP、WSON、TFBGA和PDIP等多种封装类型，尺寸从208mil到300mil不等，满足不同应用场景的尺寸需求。 5. **保护功能**: 包括芯片选择（/CS）、写保护（/WP）和保持（/HOLD）引脚，确保了数据的安全性和设备的稳定性。此外，还有复位（/RESET）引脚，用于初始化设备或恢复到默认状态。 6. **引脚配置和描述**: 文件详细列出了不同封装类型的引脚配置和功能，如SOIC/VSOP208-mil、WSON6x5-mm/8x6-mm、SOIC300-mil、TFBGA8x6-mm和PDIP300-mil等，便于用户根据具体应用选择合适的封装。 7. **功能描述**: 详细解释了各个引脚的作用，如Chip Select (/CS)用于选择器件，Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)用于数据传输，Write Protect (/WP)用于防止意外写入，HOLD (/HOLD)用于暂停设备操作，Serial Clock (CLK)提供时钟信号，Reset (/RESET)用于设备复位。 8. **块图和功能描述**: 包含了设备的内部结构示意图，并详细描述了SPI/QPI操作的工作原理，包括标准SPI、双SPI、四SPI和QPI指令集，以及 Hold 功能等，这些信息对于理解和编程控制该器件至关重要。华邦W25Q128FV是一款高效、低功耗且功能丰富的串行闪存，适合于各种嵌入式系统、物联网设备、数据存储和代码执行等应用场景。其强大的接口支持和优化的功耗设计，使其成为对性能和效率有高要求的系统的理想选择。

W25Q128FV

- 15 -

6.2 Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern, the W25Q128FV

provides several means to protect the data from inadvertent writes.

6.2.1 Write Protect Features

• Device resets when VCC is below threshold

• Time delay write disable after Power-up

• Write enable/disable instructions and automatic write disable after erase or program

• Software and Hardware (/WP pin) write protection using Status Registers

• Additional Individual Block/Sector Locks for array protection

• Write Protection using Power-down instruction

• Lock Down write protection for Status Register until the next power-up

• One Time Program (OTP) write protection for array and Security Registers using Status Register

* Note: This feature is available upon special order. Please contact Winbond for details.

Upon power-up or at power-down, the W25Q128FV will maintain a reset condition while VCC is below the

threshold value of V

WI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all

operations are disabled and no instructions are recognized. During power-up and after the VCC voltage

exceeds V

WI, all program and erase related instructions are further disabled for a time delay of tPUW. This

includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status

the VCC-min level and t

VSL time delay is reached, and it must also track the VCC supply level at power-

down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to

accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write

Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector

Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a

program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-

disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting the

Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP[2:0]) bits. These settings

allow a portion or the entire memory array to be configured as read only. Used in conjunction with the

Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware

control. See Status Register section for further information. Additionally, the Power-down instruction offers

an extra level of write protection as all instructions are ignored except for the Release Power-down

instruction.

The W25Q128FV also provides another Write Protect method using the Individual Block Locks. Each

64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the

top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is

0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or

Program commands issued to the corresponding sector or block will be ignored. When the device is

powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from

Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector

or block.

The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When

WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of

the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.

W25Q128FV

Publication Release Date: October 01, 2012

- 16 - Revision D

7. STATUS AND CONFIGURATION REGISTERS

Three Status and Configuration Registers are provided for W25Q128FV. The Read Status Register-1/2/3

instructions can be used to provide status on the availability of the flash memory array, whether the device

is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status,

Erase/Program Suspend status, output driver strength, power-up and current Address Mode. The Write

Status Register instruction can be used to configure the device write protection features, Quad SPI setting,

Security Register OTP locks, Hold/Reset functions, output driver strength and power-up Address Mode.

Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits

(SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin.

7.1 Status Registers

Figure 4a. Status Register-1

7.1.1 Erase/Write In Progress (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a

Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or

Erase/Program Security Register instruction. During this time the device will ignore further instructions

except for the Read Status Register and Erase/Program Suspend instruction (see t

W, tPP, tSE, tBE, and

CE in AC Characteristics). When the program, erase or write status/security register instruction has

completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

7.1.2 Write Enable Latch (WEL) – Status Only

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a

Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write

disable state occurs upon power-up or after any of the following instructions: Write Disable, Page

Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase

Security Register and Program Security Register.

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and

S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status

W in AC characteristics). All, none or a portion of the memory array can be

protected from Program and Erase instructions (see Status Register Memory Protection table). The

factory default setting for the Block Protection Bits is 0, none of the array protected.

W25Q128FV

- 17 -

7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the

Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.

The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction

depending on the state of the SRP0, SRP1 and WEL bits.

7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect

either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array

as shown in the Status Register Memory Protection table. The default setting is SEC=0.

7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in

conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once

CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For

instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when

CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please

refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register

(S8 and S7). The SRP bits control the method of write protection: software protection, hardware

protection, power supply lock-down or one time programmable (OTP) protection.

SRP1 SRP0 /WP

Status

Description

0 0 X

Software

Protection

/WP pin has no control. The Status register can be written to

after a Write Enable instruction, WEL=1. [Factory Default]

0 1 0

Hardware

Protected

When /WP pin is low the Status Register locked and cannot

be written to.

0 1 1

Hardware

Unprotected

When /WP pin is high the Status register is unlocked and can

be written to after a Write Enable instruction, WEL=1.

1 0 X

Power Supply

Lock-Down

Status Register is protected and cannot be written to again

until the next power-down, power-up cycle.

(1)

1 1 X

One Time

Program

(2)

Status Register is permanently protected and cannot be

written to.

Notes:

1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available upon special order. Please contact Winbond for details.

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