P2020 QorIQ处理器设计检查列表与调试指南

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"AN4261.pdf 是一份由Freescale Semiconductor发布的应用笔记，主要针对基于P2020 QorIQ集成处理器的新设计提供设计检查清单。这份文档详细阐述了如何简化设计初期阶段，以及在电源设计、复位配置、调试与测试接口、设备引脚测试点、时钟引脚、DDR接口、DMA接口、DUART接口和eSDHC及eSPI接口等多个关键方面的重要考虑事项。其目标是帮助设计师在系统启动初期就能关注到那些可能影响性能和稳定性的设计细节，同时也能用于新设计系统的调试工作。文档最后一页提供了更新信息的网站链接，以获取最新的文档版本。" 本文档的核心知识点包括： 1. **简化设计初期阶段**：文档首先强调了简化设计初期阶段的重要性，提供了指导原则和步骤，以确保设计过程的高效性和可实施性。 2. **电源设计考量**：在第2部分，讨论了电源设计的关键因素，如电源管理、功耗优化和电源分布，这些都是保证系统稳定运行的基础。 3. **复位和复位配置**：第3部分详细介绍了电源上电复位(Power-on Reset, POR)和复位配置，这些对于系统的正确初始化至关重要。 4. **调试和测试接口引脚建议**：在第4部分，文档给出了调试接口和测试引脚的推荐使用方法，以帮助识别和解决潜在问题。 5. **设备引脚与推荐测试点**：这部分详细列出了不同功能的设备引脚，以及在验证设计时应关注的测试点，有助于确保每个组件的正确连接和功能。 6. **时钟引脚推荐**：时钟信号对系统性能有直接影响，第7部分提供了关于时钟引脚选择和布局的建议，以保证时序正确。 7. **DDR接口引脚推荐**：考虑到P2020处理器可能用到的DDR内存，文档第8部分给出了关于DDR接口引脚的详细指南，确保内存数据传输的稳定。 8. **DMA接口引脚建议**：DMA(Direct Memory Access)接口允许外围设备直接访问内存，第9部分提供了关于如何优化DMA接口设计的建议。 9. **DUART接口引脚推荐**：双通用异步收发器(DUART)接口用于串行通信，第10部分给出了相关的引脚配置指导。 10. **eSDHC接口引脚建议**：这部分涉及eSDHC(Extended Secure Digital Host Controller)接口，指导如何正确配置以支持存储卡的高速数据传输。 11. **eSPI接口引脚推荐**：eSPI（Enhanced Serial Peripheral Interface）是一种低功耗的串行总线接口，第11部分给出了关于配置eSPI接口的注意事项。这份文档对于基于P2020 QorIQ处理器的系统设计人员来说是一份宝贵的参考资料，它涵盖了从设计初期到系统调试的各个环节，旨在确保设计的成功和系统的可靠性。

P2020 QorIQ Integrated Processor Design Checklist, Rev. 1

Freescale Semiconductor 7

Power Design Considerations

• The capacitors should be placed as close as possible to the processor. The capacitors need to be

selected to work well with the power-supply so as to be able to handle the P2020’s dynamic load

requirements.

2.3 SerDes Block Power Supply Decoupling

If the SerDes module is used, it requires a clean, tightly regulated source of power (SV

and XV

) to

ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling

scheme is outlined below.

• Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to

power and ground should be done with multiple vias to further reduce inductance.

• Board should have at least one 0.1 F SMT ceramic chip capacitors as close as possible for each

supply ball of the device. Where the board has blind vias, these capacitors should be placed directly

below the chip supply and ground connections. Where the board does not have blind vias, these

capacitors should be placed in a ring around the device as close to the supply and ground

connections as possible.

• There should be a 10-µF ceramic chip capacitor on the power plane of the SVDD and/or XVDD

planes, on the sides of the device where those planes are present. This should be done for all SerDes

supplies.

2.4 Power Supplies Checklist

Table 3. Power Supplies Checklist for Designer

Item

Customer

Comments

Completed

1. V

, AV

_n, XV

, and SV

power supplies have a voltage tolerance no greater than 3% from

the nominal value. Refer to the hardware specification for more details.

——

2. All other power supplies have a voltage tolerance no greater than 5% from the nominal value. Refer

to the hardware specification for more details.

——

3. Power supply selected is based on MAXIMUM power dissipation. Refer to the hardware

specification for more details.

——

4. Thermal design is based on THERMAL power dissipation. Refer to the hardware specification for

more details.

——

5. Power-up sequence is within 50 ms. Refer to the hardware specification for more details. — —

6. Recommend using large power planes to the extent possible. — —

7. Recommended PLL filter circuit is applied to AV

_PLAT, AV

_CORE0, AV

_CORE1,

_DDR, and AV

_LBIU.

——

8. If SerDes is enabled, the recommended PLL filter circuit is applied to AV

_SRDS, respectively.

Otherwise, a filter is not required.

——

9. PLL filter circuits are placed as close to the respective AV

pin as possible. — —

10. Decoupling capacitors of 0.1 µF are placed at each V

, B/G/L/C/OV

pin. — —

P2020 QorIQ Integrated Processor Design Checklist, Rev. 1

8 Freescale Semiconductor

Power-on Reset and Reset Configurations

3 Power-on Reset and Reset Configurations

3.1 Configuration and Timing

Various device functions are initialized by sampling certain signals during the assertion of HRESET. These

power-on reset (POR) inputs are pulled either high or low during this period. While these pins are generally

output pins during normal operation, they are treated as inputs while HRESET

is asserted. HRESET must

be asserted for a minimum on 100 s. When HRESET de-asserts, the configuration pins are sampled and

latched into registers, and the pins then take on their normal output circuit characteristics.

Most of the configuration pins have an internally gated 20 k nominal pull-up resistor, enabled only during

HRESET. For those configurations in which the default state is desired, no external pull-up is required.

Otherwise, a 4.7 k pull-down resistor is recommended to pull the configuration pin to a valid logic low

level. In cases where a configuration pin has no default, 4.7 k pull-up or pull-down resistors are

recommended for appropriate configuration of the pin.

An alternative to using pull-up and pull-down resistors to configure the POR pins is to use a PLD or similar

device that drives the configuration signals to the P2020 when HRESET is asserted. The PLD must begin

to drive these signals at least four SYSCLK cycles prior to the de-assertion of HRESET (PLL

configuration inputs must meet a 100 s set-up time to HRESET), hold their values for at least 2 SYSCLK

cycles after the de-assertion of HRESET, and then release the pins to high impedance afterward for normal

device operation. Refer to the P2020 Integrated Processor Hardware Specifications for details about reset

initialization timing specifications.

3.2 Configuration Settings

The following table summarizes the customer configurable device settings. Refer to the P2020 QorIQ

Integrated Host Processor Family Reference Manual for a more detailed description of each configuration

option.

Table 4. User Configuration Options

Configuration Type Functional Pins Comments

CCB Clock PLL Ratio LA[29:31] There is no default value for this PLL ratio; these signals must

be pulled to the desired value. Refer to the “System PLL Ratio”

section in the P2020RM.

e500 Core0 PLL Ratio LBCTL, LALE,

LGPL2/LOE

/LFRE

There is no default value for this PLL ratio; these signals must

be pulled to the desired value. Refer to the “e500 Core PLL

Ratio” section in the P2020RM.

e500 Core1 PLL Ratio LWE0,

UART_SOUT1,

READY_P1

There is no default value for this PLL ratio; these signals must

be pulled to the desired value. Refer to the “e500 Core PLL

Ratio” section in the P2020RM.

DDR Controller Clock PLL

Ratio

TSEC_1588_CLK_OUT,

TSEC_1588_PULSE_OUT1,

TSEC_1588_PULSE_OUT2,

There is no default value for this PLL ratio; these signals must

be pulled to the desired value. Refer to the “DDR Controller

Clock PLL Ratio” section in the P2020RM.

Boot ROM Location TSEC1_TXD[6:4],

TSEC1_TX_ER

Default: Local Bus GPCM (16-bit ROM)

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