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首页CC2538芯片技术手册:2.4GHz IEEE 802.15.4与ZigBee应用
CC2538芯片技术手册:2.4GHz IEEE 802.15.4与ZigBee应用
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更新于2024-07-18
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"CC2538用户手册是针对2.4-GHz IEEE 802.15.4和ZigBee/IP应用的System-on-Chip解决方案,由Texas Instruments公司提供。此版本为C版,用户指南的文献编号为SWRU319C,初次发布于2012年4月,最后修订于2013年5月。手册包含了重要的出口管制警告,接收方必须遵守美国、欧盟等地区的出口管理法规,未经许可不得向受限制或禁止的地区出口或再出口产品和技术。"
**知识点详解:**
1. **CC2538芯片**: CC2538是一款高度集成的System-on-Chip(SoC)解决方案,设计用于2.4-GHz频段的无线通信,特别适用于IEEE 802.15.4标准和ZigBee/IP协议栈。这款芯片集成了微控制器单元(MCU)、无线收发器、内存和其他必要的外设,为物联网(IoT)设备提供了一站式的硬件平台。
2. **IEEE 802.15.4标准**: 这是一个定义低速无线个域网(Low-Rate Wireless Personal Area Network, LR-WPAN)的国际标准,常用于智能家居、工业自动化和传感器网络等领域。它提供了基础的无线通信规范,为ZigBee、ZigBee Pro和ZigBee IP等协议栈提供物理层和媒体访问控制层(MAC层)的支持。
3. **ZigBee**: 是基于IEEE 802.15.4标准的一种开放的、标准化的无线网络协议,主要应用于低功耗、低成本、自组织的网络,如智能家居、自动化控制和智能电网等。ZigBee IP是ZigBee协议栈的一部分,增加了IPv6支持,使得设备可以直接接入互联网。
4. **System-on-Chip (SoC)**: SoC是一种将系统的主要组件,包括处理器、内存和外设接口等,集成在单个芯片上的设计方法。这种方法降低了系统成本、功耗和体积,提高了性能和可靠性。
5. **用户指南**: 提供了CC2538芯片的详细使用说明,包括初始化、配置、编程、调试和应用示例等,是开发者进行产品开发和故障排查的重要参考资料。
6. **出口管制警告**: 用户手册中的警告提示了产品和技术可能受到美国和其他国家出口管制法规的限制,强调了在国际贸易中必须遵守相关的出口许可规定,否则可能面临法律后果。
7. **版本信息**: 版本C代表了手册的一个特定版本,文献编号SWRU319C则可能用于查找更详细的文档或更新。发布日期和修订日期表明了手册的时效性,确保开发者获取到最新的技术信息。
CC2538用户手册是为开发者提供关于CC2538 SoC的全面指南,涵盖其在2.4-GHz无线通信、ZigBee/IP应用以及相关合规性方面的详细信息,是开发无线IoT设备的关键参考资料。
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23.14 Command Strobe/CSMA-CA Processor .............................................................................. 687
23.14.1 Instruction Memory ........................................................................................... 687
23.14.2 Data Registers ................................................................................................ 687
23.14.3 Program Execution ........................................................................................... 688
23.14.4 Interrupt Requests ............................................................................................ 688
23.14.5 Random Number Instruction ................................................................................ 688
23.14.6 Running CSP Programs ..................................................................................... 688
23.14.7 CSP Registers ................................................................................................ 689
23.14.8 Instruction Set Summary .................................................................................... 690
23.14.9 Instruction Set Definition ..................................................................................... 691
23.14.9.1 DECZ ...................................................................................................... 691
23.14.9.2 DECY ..................................................................................................... 692
23.14.9.3 DECX ..................................................................................................... 692
23.14.9.4 INCZ ....................................................................................................... 692
23.14.9.5 INCY ...................................................................................................... 692
23.14.9.6 INCX ...................................................................................................... 692
23.14.9.7 INCMAXY ................................................................................................. 693
23.14.9.8 RANDXY .................................................................................................. 693
23.14.9.9 INT ......................................................................................................... 693
23.14.9.10 WAITX ................................................................................................... 693
23.14.9.11 SETCMP1 ............................................................................................... 694
23.14.9.12 WAIT W ................................................................................................. 694
23.14.9.13 WEVENT1 .............................................................................................. 694
23.14.9.14 WEVENT2 .............................................................................................. 695
23.14.9.15 LABEL ................................................................................................... 695
23.14.9.16 RPT C ................................................................................................... 695
23.14.9.17 SKIP S, C ............................................................................................... 696
23.14.9.18 STOP .................................................................................................... 696
23.14.9.19 SNOP .................................................................................................... 697
23.14.9.20 SRXON .................................................................................................. 697
23.14.9.21 STXON .................................................................................................. 697
23.14.9.22 STXONCCA ............................................................................................ 697
23.14.9.23 SSAMPLECCA ......................................................................................... 698
23.14.9.24 SRFOFF ................................................................................................. 698
23.14.9.25 SFLUSHRX ............................................................................................. 698
23.14.9.26 SFLUSHTX ............................................................................................. 698
23.14.9.27 SACK .................................................................................................... 698
23.14.9.28 SACKPEND ............................................................................................. 699
23.14.9.29 SNACK .................................................................................................. 699
23.14.9.30 SRXMASKBITSET ..................................................................................... 699
23.14.9.31 SRXMASKBITCLR ..................................................................................... 699
23.14.9.32 ISSTOP .................................................................................................. 700
23.14.9.33 ISSTART ................................................................................................ 700
23.14.9.34 ISRXON ................................................................................................. 700
23.14.9.35 ISRXMASKBITSET .................................................................................... 700
23.14.9.36 ISRXMASKBITCLR .................................................................................... 701
23.14.9.37 ISTXON ................................................................................................. 701
23.14.9.38 ISTXONCCA ............................................................................................ 701
23.14.9.39 ISSAMPLECCA ........................................................................................ 701
23.14.9.40 ISRFOFF ................................................................................................ 702
23.14.9.41 ISFLUSHRX ............................................................................................ 702
23.14.9.42 ISFLUSHTX ............................................................................................. 702
23.14.9.43 ISACK ................................................................................................... 702
16
Contents SWRU319C–April 2012–Revised May 2013
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23.14.9.44 ISACKPEND ............................................................................................ 702
23.14.9.45 ISNACK ................................................................................................. 703
23.14.9.46 ISCLEAR ................................................................................................ 703
23.15 Register Settings Update ............................................................................................... 703
23.16 Radio Registers .......................................................................................................... 704
23.16.1 RFCORE_FFSM Registers ................................................................................. 704
23.16.1.1 RFCORE_FFSM Registers Mapping Summary ..................................................... 704
23.16.1.2 RFCORE_FFSM Register Descriptions .............................................................. 705
23.16.2 RFCORE_XREG Registers ................................................................................. 712
23.16.2.1 RFCORE_XREG Registers Mapping Summary ..................................................... 712
23.16.2.2 RFCORE_XREG Register Descriptions .............................................................. 715
23.16.3 RFCORE_SFR Registers ................................................................................... 748
23.16.3.1 RFCORE_SFR Registers Mapping Summary ....................................................... 749
23.16.3.2 RFCORE_SFR Register Descriptions ................................................................ 749
23.16.4 CCTEST Registers ........................................................................................... 752
23.16.4.1 CCTEST Registers Mapping Summary .............................................................. 752
23.16.4.2 CCTEST Register Descriptions ........................................................................ 752
23.16.5 ANA_REGS Registers ....................................................................................... 757
23.16.5.1 ANA_REGS Registers Mapping Summary ........................................................... 757
23.16.5.2 ANA_REGS Register Descriptions .................................................................... 757
24 Voltage Regulator ............................................................................................................ 759
A Available Software ........................................................................................................... 760
A.1 SmartRF™ Studio Software for Evaluation (www.ti.com/smartrfstudio) .......................................... 761
A.2 TIMAC Software (www.ti.com/timac) .................................................................................. 761
A.3 Z-Stack™ Software (www.ti.com/z-stack) ............................................................................ 761
B Abbreviations .................................................................................................................. 763
C Additional Information ...................................................................................................... 766
C.1 Texas Instruments Low-Power RF Web Site ......................................................................... 767
C.2 Low-Power RF Online Community ..................................................................................... 767
C.3 Texas Instruments Low-Power RF Developer Network ............................................................. 767
C.4 Low-Power RF eNewsletter ............................................................................................. 767
D References ...................................................................................................................... 768
E Revision History .............................................................................................................. 769
E.1 Revision History – External ............................................................................................. 769
17
SWRU319C–April 2012–Revised May 2013 Contents
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List of Figures
1-1. CC2538 Block Diagram................................................................................................... 34
2-1. CPU Block Diagram....................................................................................................... 47
2-2. TPIU Block Diagram ...................................................................................................... 48
2-3. Cortex-M3 Register Set................................................................................................... 50
3-1. SRD Use Example ........................................................................................................ 71
4-1. Bit-Band Mapping ........................................................................................................ 161
4-2. Data Storage.............................................................................................................. 162
5-1. Vector Table .............................................................................................................. 171
5-2. Exception Stack Frame ................................................................................................. 173
6-1. Test/Debug System Top Level Diagram .............................................................................. 178
7-1. Flow Diagram for Operational Modes ................................................................................. 186
7-2. Simple Flow Diagram for Power Management....................................................................... 188
7-3. Timing Example for Transition from 32 MHz to PM's ............................................................... 190
7-4. Simplified Figure of Current Consumption in PM1 .................................................................. 192
7-5. Simplified Figure of Current Consumption in PM2 and PM3....................................................... 192
7-6. Block Diagram Oscillators and Clocks ................................................................................ 193
8-1. Flash Write Using DMA ................................................................................................. 218
9-1. Digital I/O Pads (The Diagram Shows One of 32 Possible I/O Pins) ............................................. 233
9-2. GPIODATA Write Example ............................................................................................. 234
9-3. GPIODATA Read Example ............................................................................................. 234
9-4. PAD Configuration Override Registers................................................................................ 237
10-1. μDMA Block Diagram ................................................................................................... 287
10-2. Example of Ping-Pong μDMA Transaction ........................................................................... 293
10-3. Memory Scatter-Gather, Setup and Configuration .................................................................. 295
10-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................................... 296
10-5. Peripheral Scatter-Gather, Setup and Configuration................................................................ 298
10-6. Peripheral Scatter-Gather, μDMA Copy Sequence ................................................................. 299
11-1. GPTM Module Block Diagram.......................................................................................... 319
11-2. Input Edge-Count Mode Example, Counting Down ................................................................. 323
11-3. Input Edge-Time Mode Example....................................................................................... 324
11-4. 16-bit PWM Mode Example ............................................................................................ 326
11-5. CCP Output, GPTIMER_TnMATCHR > GPTIMER_TnILR ........................................................ 326
11-6. CCP Output, GPTIMER_TnMATCHR = GPTIMER_TnILR ........................................................ 327
11-7. CCP Output, GPTIMER_TnILR > GPTIMER_TnMATCHR ........................................................ 327
11-8. Timer Daisy-Chain ....................................................................................................... 328
13-1. Sleep timer Capture ..................................................................................................... 364
15-1. ADC Block Diagram ..................................................................................................... 374
16-1. Basic Structure of the RNG............................................................................................. 382
17-1. Analog Comparator ...................................................................................................... 386
18-1. UART Module Block Diagram .......................................................................................... 390
18-2. UART Character Frame................................................................................................. 391
18-3. LIN Message.............................................................................................................. 393
18-4. LIN Synchronization Field............................................................................................... 394
19-1. SSI Module Block Diagram ............................................................................................. 416
19-2. TI Synchronous Serial Frame Format (Single Transfer)............................................................ 419
19-3. TI Synchronous Serial Frame Format (Continuous Transfer)...................................................... 419
19-4. Freescale SPI Format (Single Transfer) With SPO = 0 and SPH = 0 ............................................ 420
18
List of Figures SWRU319C–April 2012–Revised May 2013
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19-5. Freescale SPI Format (Continuous Transfer) With SPO = 0 and SPH = 0 ...................................... 420
19-6. Freescale SPI Frame Format With SPO = 0 and SPH = 1......................................................... 421
19-7. Freescale SPI Frame Format (Single Transfer) With SPO = 1 and SPH = 0.................................... 421
19-8. Freescale SPI Frame Format (Continuous Transfer) With SPO = 1 and SPH = 0.............................. 422
19-9. Freescale SPI Frame Format With SPO = 1 and SPH = 1......................................................... 422
19-10. MICROWIRE Frame Format (Single Frame)......................................................................... 423
19-11. MICROWIRE Frame Format (Continuous Transfer) ................................................................ 424
19-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ..................................... 424
20-1. I
2
C Block Diagram........................................................................................................ 435
20-2. I
2
C Bus Configuration.................................................................................................... 436
20-3. Start and Stop Conditions............................................................................................... 436
20-4. Complete Data Transfer With a 7-Bit Address ....................................................................... 437
20-5. R/S Bit in First Byte...................................................................................................... 437
20-6. Data Validity During Bit Transfer on the I
2
C Bus..................................................................... 437
20-7. Master Single TRANSMIT .............................................................................................. 440
20-8. Master Single RECEIVE ................................................................................................ 441
20-9. Master TRANSMIT With Repeated Start Condition ................................................................. 442
20-10. Master RECEIVE With Repeated Start Condition ................................................................... 443
20-11. Master RECEIVE With Repeated Start After TRANSMIT With Repeated Start Condition..................... 444
20-12. Master TRANSMIT With Repeated Start After RECEIVE With Repeated Start Condition..................... 445
20-13. Slave Command Sequence ............................................................................................ 446
21-1. USB Controller Block Diagram ......................................................................................... 458
21-2. USB Interrupt Service Routine ......................................................................................... 460
21-3. Endpoint 0 States ........................................................................................................ 465
21-4. Endpoint 0 Service Routine............................................................................................. 466
21-5. SETUP Phase of Control Transfer..................................................................................... 468
21-6. SETUP Phase Control Transactions .................................................................................. 469
21-7. IN Data Phase for Control Transfer ................................................................................... 470
21-8. IN Phase Control Transactions......................................................................................... 471
21-9. Control Transactions Following Status Stage (TX Mode) .......................................................... 472
21-10. OUT Data Phase for Control Transfer ................................................................................ 473
21-11. OUT Phase Control Transactions...................................................................................... 474
21-12. Control Transactions Following Status Stage (RX Mode) .......................................................... 475
21-13. IN/OUT FIFOs ............................................................................................................ 476
21-14. Bulk and Interrupt IN Transactions .................................................................................... 479
21-15. Isochronous IN Transactions ........................................................................................... 481
21-16. Bulk and Interrupt OUT Transactions ................................................................................. 483
21-17. Isochronous OUT Transactions ........................................................................................ 485
22-1. Operation Sequences and Main Interrupt ............................................................................ 525
22-2. DMA Controller and Its Integration .................................................................................... 534
22-3. Symmetric Crypto Processing Steps .................................................................................. 568
22-4. Implementation of Secure HMAC Operation ......................................................................... 575
22-5. AIC: Functional Logic of one Interrupt Source ....................................................................... 591
23-1. Modulation ................................................................................................................ 664
23-2. I and Q Phases When Transmitting a Zero-Symbol Chip Sequence, t
C
= 0.5 μs ............................... 665
23-3. Schematic View of the IEEE 802.15.4 Frame Format .............................................................. 665
23-4. Format of the Frame Control Field (FCF)............................................................................. 666
23-5. Frame Data Written to the TX FIFO ................................................................................... 667
23-6. TX Flow.................................................................................................................... 669
19
SWRU319C–April 2012–Revised May 2013 List of Figures
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23-7. Transmitted Synchronization Header.................................................................................. 670
23-8. FCS Hardware Implementation ........................................................................................ 671
23-9. SFD Signal Timing....................................................................................................... 673
23-10. Filtering Scenarios (Exceptions Generated During Reception) .................................................... 675
23-11. Matching Algorithm for Short and Extended Addresses ............................................................ 677
23-12. Interrupts Generated by Source Address Matching ................................................................. 678
23-13. Data in RX FIFO for Different Settings................................................................................ 679
23-14. Acknowledge Frame Format ........................................................................................... 679
23-15. Acknowledgement Timing............................................................................................... 680
23-16. Command Strobe Timing ............................................................................................... 680
23-17. Behavior of FIFO and FIFOP Signals ................................................................................. 682
23-18. Main FSM ................................................................................................................. 684
23-19. FFT of the Random Bytes .............................................................................................. 685
23-20. Histogram of 20 Million Bytes Generated With the RANDOM Instruction ........................................ 686
23-21. Running a CSP Program................................................................................................ 689
20
List of Figures SWRU319C–April 2012–Revised May 2013
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Copyright © 2012–2013, Texas Instruments Incorporated
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