RMII规范：低引脚数接口降低交换芯片成本

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RMII (Reduced Media Independent Interface) 是一种专为在以太网物理层 (PHY) 和交换应用特定集成电路 (Switch ASIC) 之间提供低成本连接而设计的接口标准。最初发布于1998年3月20日的版本1.2，RMII规格的出现是为了应对随着网络设备端口数量增长，传统MII (Media Independent Interface) 的引脚数增加所带来成本问题。 MII原本在IEEE 802.3u标准中定义，提供了16个引脚用于数据传输和控制，这对于包含多个MAC (Media Access Controller) 或多种PHY接口的设备，如现代交换机，当增加端口数量时，引脚数的增加会显著增加成本。一个典型的12到24端口交换机可能需要处理6个引脚（每个端口）和额外的开关ASIC引脚，这使得RMII规格显得尤为重要，因为它旨在减少引脚需求，节省空间和成本。在12端口情况下，RMII可以节约大约119个引脚，同时节省额外支持这些引脚所需的电源和地线。 RMII设计的主要目标是为MII提供一个低成本的替代方案。从架构上看，RMII增加了与MII相对应的额外一致性层，允许在没有MII的情况下实现，从而扩展了灵活性。然而，它保持了对MDIO (Management Data Input/Output) 和 MDC (Management Data Clock) 管理接口的支持，这部分接口与IEEE 802.3u标准中的定义相同，确保了与现有设备的兼容性。 RMII通过简化接口设计，降低了硬件成本，对于大规模生产的交换机产品具有吸引力，使得制造商能够提供功能丰富的低成本解决方案。尽管RMII不完全取代MII，但作为其精简版本，它在现代网络基础设施中的作用不容忽视，尤其是在追求效率和成本效益的商业环境中。随着技术的发展，RMII可能会进一步演化，适应更高的速度和更复杂的网络需求，继续在通信领域发挥重要作用。

Signal Definition

RMII

Specification Rev. 1.2

5.0 Signal Definition

The PHY shall implement and conform to the requirements for REF_CLK, CRS_DV,

RXD[1:0], TX_EN, TXD[1:0], and RX_ER. The MAC interface shall implement and

conform to the requirements for REF_CLK, CRS_DV, RXD[1:0], TX_EN and

TXD[1:0].

5.1 REF_CLK

Reference Clock

REF_CLK is a continuous clock that provides the timing reference for CRS_DV,

RXD[1:0], TX_EN, TXD[1:0], and RX_ER. REF_CLK is sourced by the MAC or an

external source. Switch implementations may choose to provide REF_CLK as an input

or an output depending on whether they provide a REF_CLK output or rely on an exter-

nal clock distribution device. Each PHY device shall have an input corresponding to this

clock but may use a single clock input for multiple PHYs implemented on a single IC.

The REF_CLK frequency shall be 50 MHz +/- 50 ppm with a duty cycle between 35%

and 65% inclusive. It is assumed that the PHY uses REF_CLK as the network clock

such that no buffering is required on the transmit data path.

While the PHY may recover clock from the incoming data stream, the receiver shall

account for differences between the local REF_CLK and the recovered clock through

use of sufficient elasticity buffering. The elasticity buffer design shall not affect the

Inter-Packet Gap (IPG) for received IPGs of 36 bits or greater. To tolerate the clock vari-

ations specified here for Ethernet MTUs, the elasticity buffer shall tolerate a minimum

of +/-10 bits.* This implies that the FIFO is at least 20 bits deep and does not transfer

recovered data onto RXD[1:0] until the FIFO is half full.

*Note:Some vendors desire toleration of MTUs greater than the Ethernet MTU.

TABLE 1.

RMII

Specification Signals

Signal

Name

Direction

(with respect

to the PHY)

Direction (with

respect to the

MAC) Use

REF_CLK Input Input or Output Synchronous clock reference for receive,

transmit and control interface

CRS_DV Output Input Carrier Sense/Receive Data Valid

RXD[1:0] Output Input Receive Data

TX_EN Input Output Transmit Enable

TXD[1:0] Input Output Transmit Data

RX_ER Output Input (Not

required)

Receive Error

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