三星K5N5629ABA-AD11 MCP闪存规格及注意事项

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本文档详细介绍了三星(K5N5629ABA-AD11)型号的MCP (Multi-Chip Package) Flash Memory。该产品是一款由三星电子生产的嵌入式存储解决方案，它结合了256Mb Mux NOR Flash和额外的128Mb Mux UT RAM（Ultra-Tightly Coupled RAM），旨在提供高效能和大容量数据存储。首先，产品修订版本为0.0，发布日期为2008年11月，这表明这是该产品的早期版本，可能后续会有更新。MCP的设计目标是满足特定应用的需求，通过将多个芯片集成在一个封装中，实现了更高的密度和更小的尺寸，对于系统设计师来说，这有助于优化硬件布局和减少主板空间占用。在技术规格方面，256Mb Mux NOR Flash具有非易失性存储特性，适用于需要长期存储数据的应用场景，如操作系统、固件更新或程序代码。而128Mb Mux UT RAM则提供快速的数据存取速度，通常用于处理实时数据或者频繁访问的临时数据存储，它与NOR Flash配合使用，提高了整体系统的性能。值得注意的是，三星电子保留了更改产品规格的权利，这意味着用户在设计阶段应确保查阅最新文档以获取最准确的产品特性和限制。文档还强调，本资料仅作为参考，不构成任何知识产权许可，所有信息都是“按现状”提供，没有保证或保修，用户在使用时需自行承担风险。此外，文档提醒读者，三星产品并不适合用于生命支持、医疗、安全设备等关键领域，以及军事或国防应用，因为产品故障可能导致严重后果。如果产品用于政府采购，可能需要遵循特殊的条款或规定。对于三星产品的最新信息和更新，建议直接联系最近的三星办事处查询。 K5N5629ABA-AD11是一款针对特定应用设计的MCP Flash Memory，提供了高性能和大容量存储，但使用时必须考虑到其规格限制、适用范围和三星的维护政策。对于系统集成者而言，理解和遵循这些信息至关重要。

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asserting CE high.

3.1.2.2 8-, 16-Word Linear Burst Read

As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap & no-wrap mode, in which a fixed number of words are

read from consecutive addresses. In these modes, the addresses for burst read are determined by the group within which the starting

address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode.(See Table. 6)

Table 7: Burst Address Groups(Wrap mode only)

As an example: In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the

wrap burst sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to

the first address in the selected group. In a similar manner, 16-word wrap mode begin their burst sequence on the starting address written to

the device, and then wrap back to the first address in the selected address group.

In no-wrap mode case, if the starting address in the 8-word mode is 2h, the no-wrap burst sequence would be 2-3-4-5-6-7-8-9h. The burst

sequence begins with the starting address written to the device, and continue to the 8th address from starting address. In a similar manner,

16-word no-wrap mode begin their burst sequence on the starting address written to the device, and continue to the 16th address from starting

address. Also, when the address cross the word boundary in no-wrap mode, same number of additional clock cycles as continuous linear

mode is needed.

3.1.3 Programmable Wait State

The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven from

low to high for burst read mode. Upon power up, the number of total initial access cycles defaults to fourteen.

3.1.4 Handshaking

The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst

data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait state configura-

tion.(See "Set Burst Mode Configuration Register" for details.) The rising edge of RDY after OE

goes low indicates the initial word of valid

burst data. Using the autoselect command sequence the handshaking feature may be verified in the device.

3.2 Set Burst Mode Configuration Register

The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. The

burst mode configuration register must be set before the device enter burst mode.

The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h, address

bits A10-A0 should be 101_0101_0101b, and address bits A18-A11 set the code to be latched. The device will power up or after a hardware

reset with the default setting.

Burst Mode Group Size Group Address Ranges

8 word 8 words

0-7h, 8-Fh, 10-17h, ....

16 word 16words 0-Fh, 10-1Fh, 20-2Fh, ....

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Table 8: Burst Mode Configuration Register Table

NOTE

Initial wait state should be set according to it’s clock frequency. Table7 recommend the program wait state for each clock frequencies.

Not 100% tested

3.2.1 Programmable Wait State Configuration

This feature informs the device the number of clock cycles that must elapse after AVD is driven from low to high before data will be available.

This value is determined by the input frequency of the device. Address bits A14-A11 determine the setting. (See Burst Mode Configuration

Register Table) The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in

burst mode. Note that hardware reset will set the wait state to the default setting, that is 14 initial cycles.

3.2.2 Burst Read Mode Setting

The device supports five different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap and 8 and 16 word

linear burst modes with no-wrap.

3.2.3 RDY Configuration

By default, the RDY pin will be high whenever there is valid data on the output. The device can be set so that RDY goes active one data cycle

before active data. Adddress bit A18 determine this setting. The RDY pin behaves same way in word boundary crossing case.

Table 9: Burst Address Sequences

Address Bit Function Settings(Binary)

A19 Read Mode

1 = Synchronous Burst Read Mode

0 = Asynchronous Read Mode (default)

A18 RDY Active

1 = RDY active one clock cycle before data

0 = RDY active with data(default)

A17

Burst Read Mode

000 = Continuous(default)

001 = 8-word linear with wrap

010 = 16-word linear with wrap

011 = 8-word linear with no-wrap

100 = 16-word linear with no-wrap

101~111 = Reserve

A16

A15

A14

Programmable Wait State

0000 = Data is valid on the 4th active CLK edge after AVD

transition to VIH(40MHz)

0001 = Data is valid on the 5th active CLK edge after AVD

transition to VIH(50MHz)

0010 = Data is valid on the 6th active CLK edge after AVD

transition to VIH(54/60MHz)

0011 = Data is valid on the 7th active CLK edge after AVD

transition to VIH(66/70MHz)

0100 = Data is valid on the 8th active CLK edge after AVD

transition to VIH(80MHz)

0101 = Data is valid on the 9th active CLK edge after AVD

transition to VIH(83/90MHz)

0110 = Data is valid on the 10th active CLK edge after AVD

transition to VIH(100MHz)

0111 = Data is valid on the 11th active CLK edge after AVD

transition to VIH(108/110MHz)

1000 = Data is valid on the 12th active CLK edge after AVD

transition to VIH(120MHz)

1001 = Data is valid on the 13th active CLK edge after AVD

transition to VIH

1010 = Data is valid on the 14th active CLK edge after AVD transition to VIH(default, at 133MHz)

1011 = Data is valid on the 15th active CLK edge after AVD

transition to VIH

1100~1111 = Reserve

A13

A12

A11

Start

Addr.

Burst Address Sequence(Decimal)

Continuous Burst 8-word Burst 16-word Burst

Wrap

0 0-1-2-3-4-5-6... 0-1-2-3-4-5-6-7 0-1-2-3 ... -D-E-F

1 1-2-3-4-5-6-7... 1-2-3-4-5-6-7-0 1-2-3-4 ... -E-F-0

2 2-3-4-5-6-7-8... 2-3-4-5-6-7-0-1 2-3-4-5 ... -F-0-1

No-wrap

0 0-1-2-3-4-5-6... 0-1-2-3-4-5-6-7 0-1-2-3 ... -D-E-F

1 1-2-3-4-5-6-7... 1-2-3-4-5-6-7-8 1-2-3-4 ... -E-F-10

2 2-3-4-5-6-7-8... 2-3-4-5-6-7-8-9 2-3-4-5 ... -F-10-11

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3.3 Autoselect Mode

By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asyn-

chronous read mode. The system can then read autoselect codes from the internal register(which is separate from the memory array). Stan-

dard asynchronous read cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by

reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection. Table 5 shows the address

and data requirements. The autoselect command sequence may be written to an address within a bank that is in the read mode, erase-sus-

pend-read mode or program-suspend-read mode. The autoselect command may not be written while the device is actively programming or

erasing in the device. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle

that contains the address and the autoselect command. Note that the block address is needed for the verification of block protection. The sys-

tem may read at any address within the same bank any number of times without initiating another autoselect command sequence. And the

burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation, write Reset command(F0H) into the command

Table 10: Autoselect Mode Description

4 Standby Mode

When the CE inputs is held at VCC ± 0.2V, and the system is not reading or writing, the device enters Stand-by mode to minimize the power

consumption. In this mode, the device outputs are placed in the high impedence state, independent of the OE

input. When the device is in

either of these standby modes, the device requires standard access time (tCE ) for read access before it is ready to read data. If the device is

deselected during erasure or programming, the device draws active current until the operation is completed. I

CC5 in the DC Characteristics

table represents the standby current specification.

4.1 Automatic Sleep Mode

The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When

addresses remain stable for t

AA+60ns, the device automatically enables this mode. The Automatic sleep mode is depends on the CE, WE and

signal, so CE, WE and OE signals are held at any state. In a sleep mode, output data is latched and always available to the system. When

is active, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current.

4.2 Output Disable Mode

When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.

Description Address Read Data

Manufacturer ID (DA) + 00H ECH

Device ID (DA) + 01H 2208H(Top Boot Block), 2209H(Bottom Boot Block)

Block Protection/Unprotection (BA) + 02H 01H (protected), 00H (unprotected)

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5 Block Protection & Unprotection

To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the

device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles

are written: addresses are don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while

specifying with addresses A6, A1 and A0 whether that block should be protected (A6 = V

IL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 =

IH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset

command).

The device offers three types of data protection at the block level:

• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.

• When WP

is at VIL, the two outermost blocks are protected.

• When V

PP is at VIL, all blocks are protected.

Note that user never float the V

pp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.

6 Hardware Reset

The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period

of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration

of the RESET

pulse. The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted

operation should be reinitiated once the device is ready to accept another command sequence. As previously noted, when RESET

is held at

Vss ± 0.2V, the device enters standby mode. The RESET

pin may be tied to the system reset pin. If a system reset occurs during the Internal

Program or Erase Routine, the device will be automatically reset to the asynchronous read mode; this will enable the systems microprocessor

to read the boot-up firmware from the Flash memory. If RESET

is asserted during a program or erase operation, the device requires a time of

tREADY (during Internal Routines) before the device is ready to read data again. If RESET

is asserted when a program or erase operation is

not executing, the reset operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data after

RESET

returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 10 for the timing diagram.

6.1 Software Reset

The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The

addresses are in Don’t Care state. The reset command may be written between the sequence cycles in an erase command sequence before

erasing begins, or in an program command sequence before programming begins. If the device begins erasure or programming, the reset

command is ignored until the operation is completed. If the program command sequence is written to a bank that is in the Erase Suspend

mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command valid between the sequence cycles

in an autoselect command sequence. In an autoselect mode, the reset command must be written to return to the read mode. If a bank entered

the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Also, if

a bank entered the autoselect mode while in the Program Suspend mode, writing the reset command returns that bank to the program-sus-

pend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode. (or

erase-suspend-read mode if the bank was in Erase Suspend)

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7 Program

The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Rou-

tine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles.

The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be pro-

grammed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin

by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During

the Internal Program Routine, commands written to the device will be ignored.

Note that a hardware reset during a program operation will cause data corruption at the corresponding location.

7.1 Accelerated Program

The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is

possible. When V

ID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any pro-

tected blocks, and uses the higher voltage on the input to reduce the time required for program operations. In accelerated program mode, the

system would use a two-cycle program command sequence for only a word program. By removing V

ID returns the device to normal operation

mode.

Note that Read While Accelerated Program and Program suspend mode are not guaranteed.

• Program/Erase cycling must be limited below 100cycles for optimum performance.

• Ambient temperature requirements : T

= 30°C±10°C

Single word accelerated program operation

The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-cycle (PA -

PD) is for program address and data)

7.2 Writer Buffer Programming

Write Buffer Programming allows the system write to a maximum of 32 words in one programming operation. This results in faster effective

programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi-ated by first writing

two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the block address in which pro-

gramming will occur. The fourth cycle writes the block address and the number of word locations, minus one, to be programmed. For example,

if the system will program 19 unique address locations, then 12h should be written to the device. This tells the device how many write buffer

addresses will be loaded with data. The number of locations to program cannot exceed the size of the write buffer or the operation will abort.

The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A23(max.) ~

A5 entered at fifth cycle. All subsequent address/ data pairs must fall within the selected write-buffer-page, so that all subsequent

addresses must have the same address bit A23(max.) ~ A5 as those entered at fifth cycle. Write buffer locations may be loaded in

any order.

Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" com mand at

the block address. Any other command address/data combination aborts the Write Buffer Programming operation. The device then begins

programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1

should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be sus-

pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the

device is ready to execute the next command. Note also that an address loaction cannot be loaded more than once into the write-buffer-page.

The Write Buffer Programming Sequence can be aborted in the following ways:

• Loading a value that is greater than the buffer size(32-words) during then number of word locations to Program step.

(In case, WC > 1FH @Table5 )

• The number of Program address/data pairs entered is different to the number of word locations initially defined with WC (@Table5)

• Writing a Program address to have a different write-buffer-page with selected write-buffer-page

( Address bits A23(max) ~ A5 are different)

• Writing non-exact "Program Buffer to Flash" command

The abort condition is indicated by DQ1 = 1, DQ7 = DATA

(for the last address location loaded), DQ6 = toggle, and DQ5=0. A "Write-to-Buffer-

Abort Reset" command sequence must be written to reset the device for the next operation. Note that the third cycle of Write-to-Buffer-Abort

Reset command sequence(XXXh-F0h) is required when using Write-Buffer-Programming features in Unlock Bypass mode. And from the third

cycle to the last cycle of Write to Buffer command is also required when using Write-Buffer-Programming features in Unlock Bypass mode. A

bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status

bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can con-

vert a “0” to a “1."

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