CMT2300A FIFO与包格式工作原理及中断系统解析

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"CMT2300A FIFO和包格式使用指南.pdf" 本文档是CMT2300A FIFO（先进先出）和包格式的使用指南，旨在详细阐述该器件的FIFO工作原理、包格式以及中断系统的工作方式。在介绍配置寄存器内容时，会关联到RFPDK平台上可输入的参数，以便用户进行配置。文档涵盖了以下部分编号的CMT2300A： - 部件编号：CMT2300A - 频率范围：127-1020MHz - 调制方式：(G)FSK/OOK - 功能：收发器 - 配置：寄存器 - 封装：QFN16 在阅读本文档之前，建议先阅读《AN142-CMT2300A快速入门指南》以更好地理解CMT2300A的基本操作。文档的主要内容包括： 1. FIFO工作原理： - FIFO相关的寄存器：这部分将详细解释与FIFO操作相关的硬件寄存器，这些寄存器用于控制数据的读写和状态查询。 - FIFO工作模式：介绍FIFO的不同工作模式，如空闲模式、接收模式和发送模式，以及如何在不同场景下切换这些模式。 2. FIFO中断时机： - FIFO在接收和发送过程中如何触发中断，以及中断处理的时序，这对于实时处理数据传输至关重要。 3. FIFO应用场景： - 应用场景1：接收数据在RX端：描述如何在接收数据时利用FIFO来存储并处理接收到的数据。 - 应用场景2：预先填充数据进入TX发射：说明如何在数据传输前预先装载FIFO，以确保连续无间断的传输。在这些应用场景中，用户将了解到如何设置和管理FIFO，以实现高效、可靠的无线通信。通过理解FIFO的工作机制和中断系统，开发者能够优化CMT2300A的性能，确保数据的正确传输和处理。这份指南对于那些需要利用CMT2300A进行无线通信设计的工程师来说是一份非常实用的参考资料，它提供了深入的技术细节和实际应用示例，有助于用户充分利用CMT2300A的FIFO功能和包格式特性。

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Cmt2300_GoStby();

Cmt2300_ClearInterruptFlags();

/* Must clear FIFO after enable SPI to read or write the FIFO */

Cmt2300_EnableWriteFifo();

Cmt2300_ClearFifo();

// When merged FIFO is used, additional delay is required when the sending byte is too long.

/* The length need be smaller than 32 */

Cmt2300_WriteFifo(g_pTxBuffer, g_nTxLength);

FIFO read-write operation code examples see Appendix 1.

1.3 FIFO Interrupt Timing

Here, we first give the interrupt timing diagram of RX FIFO and TX FIFO. Users can refer to them to

understand easily.

Figure2. CMT2300A RX FIFO Interrupt Timing Diagram

Figure3. CMT2300A TX FIFO Interrupt Timing Diagram

1.4 FIFO Application Scenes

When the FIFO is configured, you can start using it. Here are some classic application scenes. To

complete the entire process of TX and RX, you also need to configure and control other things. These are

introduced later. Here we will only introduce the contents related to FIFO.

10 32 54 76 98 1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130EMPTY FULL

RX_FIFO_NMTY

RX_FIFO_TH

RX_FIFO_FULL

Sync 10 32 54 76 98 1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130RX DATA Noise Noise

SYNC_OK

RX FIFO ARRAY

RX_FIFO_OVF

(FIFO_TH = 16)

RX_FIFO_WBYTE

10 32 54 76 98 1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130EMPTY FULL

TX_FIFO_NMTY

TX_FIFO_TH

TX_FIFO_FULL

Sync 10 32 54 76 98 1110 1312 1514 1716 1918 2120 2322 2524 2726 2928 3130TX DATA Prefix 0

FIFO ARRAY

(FIFO_TH = 16)

Pream

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1.4.1 Application scene 1: Receive the data at RX

RX FIFO is used more directly. Clear it when you enter RX every time. Enter RX and fill them if the data is

received (Detect the Sync Word successfully). MCU can achieve the following several operations according to

the interrupt. After you have finished, you cannot use it. Send FIFO_CLR_RX to clear before you receive it

next time.

1. Detect the RX_FIFO_FULL interrupt. Once valid indicates that the FIFO has been filled, you can start

reading. The appropriate packet length is just equal to the FIFO depth. Also, the user does not read the

FIFO until the full packet is received.

2. Detect the RX_FIFO_TH interrupt. Once valid indicates that the FIFO has been filled in the preset data

length, you can start reading. The appropriate packet length is not equal to the FIFO depth. Also, the

user does not read the FIFO until the full packet is received.

3. Detect the RX_FIFO_NMTY interrupt. Once valid, read immediately until the interrupt is invalid. Read

again when the interrupt is valid again. This allows you to read them while you receive them. It is suitable

for the case where the packet length is greater than the FIFO depth and is suitable for the case where

the packet length is less than or equal to the FIFO depth.

4. Detect the X_FIFO_WBYTE interrupt. Read immediately once it is valid. This allows you to achieve the

regular operation to write a byte and then read a byte. The premise is that SPI is faster than receiving the

data.

In addition, you can define how many packets are sent per sending by setting the TX_PKT_NUM <7:0>.

If sending the packet is more than one, the FIFO_AUTO_RES_EN is set to 1. That is, the TX FIFO

automatically clears the read pointer and goes back the unread state after each packet is sent. This allows

you to repeatedly send the same packet. You don't need MCU to fill in the data again. The user can set the

TX_PKT_GAP <7:0> to define the time gap between each packet, the unit is the symbol. After entering the

transmitting state, the transmitter sends N packets according to these configurations. After completing, the

transmitter automatically exits the TX and returns to the specified state. The status after exiting can be

configured by TX_EXIT_STATE <1:0>.

If you want to achieve continuous reception, it is recommended to use the above fourth operation. This

needs SPI to read quickly enough. At least it is 1.5 times faster than the rate that FIFO writes a byte. For

example, if the data rate is 10KHz, the time it takes to receive a byte is about 800 us. The rate SPI reads a

byte is 1.5 times faster than the rate FIFO writes a byte. The most time-consuming is 534us. SPI reads a byte

for 8 SCL clock cycles, but with the added time cost before and after, we can count it according to the 10 SCL

clock cycles, then each cycle is 53.4us, converted to SCL clock frequency is about 18.7 kHz. The rate of SCL

is roughly 2 times the rate of data.

1.4.2 Application scene 2: Fill in the data beforehand and enter the TX transmitting

For many applications, pre fill the data packets to be transmitted into TX FIFO, and then enter the TX

transmitting. The behavior of filling data is suggested to be executed in the STBY state. This scene is suitable

for packet length less than or equal to FIFO depth, and the application time does not need to be very compact.

After the user pre configured, he can write the data directly and judge whether the data has been fully written

by detecting the interrupt of TX_FIFO_NMTY, TX_FIFO_TH or TX_FIFO_FULL. During the debugging stage,

after completing the data, the user can read back the filling data according to the following methods, and

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