Arria V FPGA的Avalon-ST接口详解：PCIe协议设计与应用

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本文档主要介绍了Altera公司Arria V系列FPGA中的PCI Express (PCIe) 接口，特别是使用Avalon Streaming (Avalon-ST) 界面的配置方法和设计流程。Arria V FPGA集成了一个可配置的、硬化的PCIe协议栈，兼容PCI Express Base Specification 2.1或3.0标准，提供了高度灵活性，但同时也要求开发者对PCIe协议有深入理解。文章详细内容包括： 1. **功能特性**：文档首先概述了Avalon-ST接口的特点，强调其灵活性以及与PCIe协议的兼容性。对于那些希望利用该接口进行PCIe设计的用户来说，这些特性是关键。 2. **版本更新**：提到了文档最后更新的时间和所针对的 Quartus Prime 设计套件版本，确保读者使用的是最新且最适用的信息。 3. **设备家族支持**：文档列出了Arria V系列FPGA的具体型号，帮助用户确定他们的硬件是否支持PCIe接口和Avalon-ST接口。 4. **配置选项**：介绍了不同配置的选择，包括可能的接口参数设置和性能等级推荐，以优化资源利用率。 5. **设计步骤**： - **Qsys设计流程**：文档详细指导用户如何使用Quartus Prime Software中的Qsys工具进行系统级设计，包括创建系统架构、生成测试台和设计文件。 - **模拟与仿真**：通过模拟示例设计来验证接口的正确性和行为，这对于设计验证至关重要。 - **综合与编译**：解释了如何在Quartus Prime中合成设计，物理布局的理解，以及最终的编译过程。 - **修改与扩展**：指南中还包含了如何根据项目需求修改预设的示例设计，以及如何将PCIe IP核心作为单独组件通过IP Catalog导入到设计中。 6. **参数设置**：着重讨论了Avalon-ST系统的设置选项，如系统时钟、数据宽度等，这些设置直接影响到接口的性能和兼容性。这份文档为Altera Arria V FPGA的用户提供了丰富的PCIe接口设计指南，包括从入门到高级应用所需的知识和技术细节，有助于用户高效地集成和调试PCIe功能到自己的设计中。对于那些希望在FPGA上实现PCIe通信的工程师来说，这是一个不可或缺的参考资源。

Figure 1-5: Example Design Preset Parameters

• Targeted Device Family

• Lanes

• Lane Rate

• Application Clock Rate

• Port type

• Application Interface

• Tags supported

• Maximum payload size

• Number of functions

e following example designs are available for the Arria V Hard IP for PCI Express. You can download

them from the <install_dir>/ ip/altera/altera_pcie/altera_pcie_hip_ast_ec/

example_design/<dev> directory:

• pcie_de_gen1_x2_ast64.qsys

• pcie_de_gen1_x4_ast64.qsys

• pcie_de_gen1_x8_ast128.qsys

• pcie_de_rp_gen1_x4_ast64.qsys

• pcie_de_rp_gen1_x8_ast128.qsys

Click on the link below to get started with the example design provided in this user guide.

Related Information

Getting Started with the Arria V Hard IP for PCI Express on page 2-1

1-10

Example Designs

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custom or third-party BFM. e Qsys Generate menu generates simulation models. Altera supports

ModelSim

- Intel FPGA Edition for all IP. e PCIe cores support the Aldec RivieraPro, Cadence

NCsim, Mentor Graphics ModelSim, and Synopsys

VCS and VCS-MX simulators.

e Altera testbench and Root Port or Endpoint BFM provide a simple method to do basic testing of

the Application Layer logic that interfaces to the variation. However, the testbench and Root Port BFM

are not intended to be a substitute for a full verication environment. To thoroughly test your applica‐

tion, Altera suggests that you obtain commercially available PCI Express verication IP and tools, or do

your own extensive hardware testing, or both.

3. Compile your design using the Quartus Prime soware. If the versions of your design and the Quartus

Prime soware you are running do not match, regenerate your PCIe design.

4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐

ment Kits link below for a list of Altera's development boards.

5. Test the hardware. You can use Altera's SignalTap

Logic Analyzer or a third-party protocol analyzer to

observe behavior.

6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. en

repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test).

e Application Layer logic is typically called APPS.

Related Information

• Parameter Settings on page 3-1

• Getting Started with the Arria V Hard IP for PCI Express on page 2-1

• All Development Kits

• Altera Wiki PCI Express

For complete design examples and help creating new projects and specic functions, such as MSI or

MSI-X related to PCI Express. Altera Applications engineers regularly update content and add new

design examples. ese examples help designers like you get more out of the Altera PCI Express IP core

and may decrease your time-to-market. e design examples of the Altera Wiki page provide useful

guidance for developing your own design. However, the content of the Altera Wiki is not guaranteed by

Altera.

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Creating a Design for PCI Express

1-13

Datasheet

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Getting Started with the Arria V Hard IP for PCI

Express

2017.05.12

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is section provides instructions to help you quickly customize, simulate, and compile the Arria V Hard

IP for PCI Express IP Core. When you install the Quartus Prime soware you also install the IP Library.

is installation includes design examples for Hard IP for PCI Express under the <install_dir>/ip/

altera/altera_pcie/ directory.

Aer you install the Quartus Prime soware for 14.0, you can copy the design examples from the

<install_dir>/ip/altera/altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/

example_designs/<dev> directory. is walkthrough uses the Gen1 ×4 Endpoint,

pcie_de_gen1_x4_ast64.qsys. e following gure illustrates the top-level modules of the testbench in

which the DUT, a Gen1 Endpoint, connects to a chaining DMA engine, labeled APPS in the following

gure, and a Root Port model. e simulation can use the parallel PHY Interface for PCI Express (PIPE)

or serial interface.

Figure 2-1: Testbench for an Endpoint

APPS

altpcied_<dev>_hwtcl.v

Hard IP for PCI Express Testbench for Endpoints

Avalon-ST TX

Avalon-ST RX

reset

status

Avalon-ST TX

Avalon-ST RX

reset

status

DUT

altpcie_<dev>_hip_ast_hwtcl.v

Root Port Model

altpcie_tbed_<dev>_hwtcl.v

PIPE or

Serial

Interface

Root Port BFM

altpcietb_bfm_rpvar_64b_x8_pipen1b

Root Port Driver and Monitor

altpcietb_bfm_vc_intf

Altera provides example designs to help you get started with the Arria V Hard IP for PCI Express IP Core.

You can use example designs as a starting point for your own design. e example designs include scripts

to compile and simulate the Arria V Hard IP for PCI Express IP Core. is example design provides a

simple method to perform basic testing of the Application Layer logic that interfaces to the Hard IP for

PCI Express.

Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current

specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly

agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information

and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

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