RTL8363SB-CG：2+2端口千兆交换机控制器数据手册

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"RTL8363SB-CG是一款由Realtek Semiconductor Corp.生产的二层管理型2+2端口千兆以太网交换机控制器的数据表，详细规格书中包含了技术参数、功能特性以及使用注意事项等内容。" 本文将详细介绍RTL8363SB-CG的主要特性、功能和应用范围。 RTL8363SB-CG是一款专为网络设备设计的高性能芯片，它集成了2个千兆以太网物理层(PHY)接口，能够支持10/100/1000Mbps的传输速率。这款控制器在L2层提供了全面的管理能力，适用于需要智能网络控制的场景，如小型企业网络、家庭网络中心或工业自动化系统。该数据表中的主要内容可能包括以下几个部分： 1. **功能特性**：RTL8363SB-CG可能具备诸如端口镜像、VLAN（虚拟局域网）支持、QoS（服务质量）策略、IGMP（Internet Group Management Protocol） Snooping、端口安全和流量控制等高级功能。这些特性使得网络管理者能够精细控制网络流量，提高网络性能和安全性。 2. **硬件规格**：详细的技术参数，如功耗、封装尺寸、引脚定义等，这些都是设计电路板时必须考虑的关键因素。 3. **接口支持**：RTL8363SB-CG可能支持多种接口标准，如SPI（串行外围接口）用于与主机通信，MDI（媒体独立接口）用于连接网络线缆，以及其他可能的控制和状态接口。 4. **电源管理**：数据表会列出芯片的工作电压范围和电流需求，以及低功耗模式，这对于电源效率和系统散热至关重要。 5. **软件支持**：Realtek通常会提供驱动程序和API（应用程序编程接口），使得开发者能够轻松集成并控制RTL8363SB-CG的功能。 6. **兼容性与认证**：数据表可能会提及芯片与其他硬件和软件的兼容性，以及任何必要的行业标准认证，如IEEE 802.3af/at PoE（以太网供电）支持。 7. **开发与支持**：Realtek作为供应商，可能会提供开发工具、样片和详细的技术支持，帮助制造商快速设计出基于RTL8363SB-CG的产品。 RTL8363SB-CG是Realtek推出的一款强大而灵活的网络交换机控制器，通过其丰富的管理和控制功能，可以实现高效、安全的网络环境。这款芯片的详细规格书对于硬件工程师和网络设备制造商来说是一份重要的参考资料。

RTL8363SB

Datasheet

Layer 2 Managed 2+2-Port 10/100/1000M Switch Controller vii Track ID: JATR-2265-11 Rev. 1.0

ABLE 53. MII MAC MODE TIMING.............................................................................................................................................65

TABLE 54. MII PHY MODE TIMING CHARACTERISTICS................................................................................................................66

TABLE 55. RGMII TIMING CHARACTERISTICS..............................................................................................................................68

TABLE 56. POWER AND RESET CHARACTERISTICS ........................................................................................................................69

TABLE 57. ORDERING INFORMATION ............................................................................................................................................71

List of Figures

FIGURE 1. 2-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII/GMII .....................................................................................5

FIGURE 2. BLOCK DIAGRAM..........................................................................................................................................................6

FIGURE 3. PIN ASSIGNMENTS (LQFP-128) ....................................................................................................................................7

FIGURE 4. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION ..................................................................................................25

FIGURE 5. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART..................................................................................32

FIGURE 6. MAX-MIN SCHEDULING DIAGRAM ...........................................................................................................................34

FIGURE 7. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED...........................................................................38

FIGURE 8. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED...................................................................................38

FIGURE 9. SMI START AND STOP COMMAND ..............................................................................................................................40

FIGURE 10. EEPROM SMI HOST TO EEPROM............................................................................................................................40

FIGURE 11. EEPROM SMI HOST MODE FRAME...........................................................................................................................40

FIGURE 12. EEPROM SMI WRITE COMMAND FOR SLAVE MODE ................................................................................................41

FIGURE 13. EEPROM SMI READ COMMAND FOR SLAVE MODE..................................................................................................41

FIGURE 14. SPI-SLAVE WRITE COMMAND ACCESS FORMAT ........................................................................................................42

FIGURE 15. SPI-SLAVE READ COMMAND ACCESS FORMAT .........................................................................................................42

FIGURE 16. MAC GMII MODE INTERFACE (1GBPS) SIGNAL DIAGRAM........................................................................................45

FIGURE 17. RGMII MODE INTERFACE SIGNAL DIAGRAM.............................................................................................................46

FIGURE 18. MII PHY MODE INTERFACE (100MBPS) SIGNAL DIAGRAM .......................................................................................48

FIGURE 19. MII MAC MODE INTERFACE (100MBPS) SIGNAL DIAGRAM......................................................................................48

FIGURE 20. EEPROM SMI HOST MODE TIMING CHARACTERISTICS............................................................................................60

FIGURE 21. SCK/SDA POWER ON TIMING ....................................................................................................................................60

FIGURE 22. EEPROM AUTO-LOAD TIMING..................................................................................................................................60

FIGURE 23. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ..........................................................................................61

FIGURE 24. SPI-SLAVE MODE TIMING CHARACTERISTICS............................................................................................................62

FIGURE 25. MDIO SOURCED BY THE MASTER ..............................................................................................................................63

FIGURE 26. MDIO SOURCED BY THE RTL8363SB (SLAVE) .........................................................................................................63

FIGURE 27. GMII TIMING CHARACTERISTICS ...............................................................................................................................64

FIGURE 28. MII MAC MODE CLOCK TO DATA OUTPUT DELAY TIMING ......................................................................................65

FIGURE 29. MII MAC MODE INPUT TIMING .................................................................................................................................65

FIGURE 30. MII PHY MODE OUTPUT TIMING...............................................................................................................................66

FIGURE 31. MII PHY MODE CLOCK OUTPUT TO DATA INPUT DELAY TIMING .............................................................................66

FIGURE 32. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=0) ................................................................67

FIGURE 33. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=2NS) ............................................................67

FIGURE 34. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=0)....................................................................67

FIGURE 35. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=2NS)................................................................68

FIGURE 36. POWER AND RESET CHARACTERISTICS.......................................................................................................................69

RTL8363SB

Datasheet

Layer 2 Managed 2+2-Port 10/100/1000M Switch Controller 1 Track ID: JATR-2265-11 Rev. 1.0

1. General Description

The RTL8363SB-CG is an LQFP128, high-performance 2+2-port 10/100/1000M Ethernet switch. It

features low-power integrated dual-port Gigabit PHYs that support 1000Base-T, 100Base-TX, and

10Base-T.

For specific applications, the RTL8363SB supports two extra interfaces that can be configured as

GMII/RGMII/MII interfaces. The RTL8363SB integrates all the functions of a high-speed switch system;

including SRAM for packet buffering, non-blocking switch fabric, and internal register management into

a single CMOS device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal

The embedded packet storage SRAM in the RTL8363SB features superior memory management

technology to efficiently utilize memory space. The RTL8363SB integrates a 2K-entry look-up table with

a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write access

from the EEPROM Serial Management Interface (SMI), Media Independent Interface Management

(MIIM), or SPI Interface. Each of the entries can be configured as a static entry. Normal entry aging time

is between 200 and 400 seconds. Eight Filtering Databases are used to provide Independent VLAN

Learning and Shared VLAN Learning (IVL/SVL) functions.

The Extension GMAC0 and Extension GMAC1 of the RTL8363SB implement dual GMII/RGMII/MII

interfaces. These interfaces could be connected to an external PHY, MAC, CPU, or RISC for specific

applications. In router applications, the RTL8363SB supports Port VID (PVID) for each port to insert a

PVID in the VLAN tag on egress. When using this function, VID information carried in the VLAN tag

will be changed to PVID.

Note: The RTL8363SB Extra Interface (Extension GMAC0 and Extension GMAC1) supports:

Dual-Port Gigabit Media Independent Interface (GMII)

Dual-Port Reduced Gigabit Media Independent Interface (RGMII)

Dual-Port Media Independent Interface (MII)

The RTL8363SB supports standard 802.3x flow control frames for full duplex, and optional backpressure

for half duplex. It determines when to invoke the flow control mechanism by checking the availability of

system resources, including the packet buffers and transmitting queues. The RTL8363SB supports

broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-blocked ports

only. For IP multicast applications, the RTL8363SB supports IPv4 IGMPv1/v2/v3 and IPv6 MLDv1/v2

snooping.

In order to support flexible traffic classification, the RTL8363SB supports 64-entry ACL rule check and

multiple actions options. Each port can optionally enable or disable the ACL rule check function. The

ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an

ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value

in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps

steps).

In Bridge operation the RTL8363SB supports 16 sets of port configurations: disable, block, learning, and

forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and

management application requirements, the RTL8363SB supports IEEE 802.1x Port-based/MAC-based

Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8363SB provides a

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