Micron DDR3L SDRAM技术规格详解

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"Micron-MT41K256M8DA-125.pdf 是 Micron 公司的一款1.35V DDR3L SDRAM (低电压双倍数据速率第三代同步动态随机存取存储器)的数据手册。该手册涵盖了不同容量的内存芯片型号，如 MT41K512M4、MT41K256M8 和 MT41K128M16，分别具有64Mb x 4 x 8 banks、32Mb x 8 x 8 banks 和 16Mb x 16 x 8 banks 的配置。" 正文: DDR3L SDRAM 是 DDR3 SDRAM 的一个变种，主要特点是工作电压降低至1.35V，这有助于减少功耗，提高能效。在某些情况下，这些设备也能在1.5V的电压下兼容运行，符合标准的 DDR3 (1.5V) SDRAM 规范。该内存芯片的主要特性包括： 1. **工作电压**：VDD 和 VDDQ 为1.35V，工作电压范围在1.283V到1.45V之间。 2. **兼容性**：与1.5V DDR3 SDRAM 后向兼容，可以在1.5V±0.075V的电压下正常工作。 3. **双向差分数据 strobe**：使用差分双向数据 strobe 提高信号质量，降低干扰。 4. **8n位预取架构**：预取技术使得数据传输更高效，这里的8n位指的是数据总线宽度的8倍。 5. **差分时钟输入**：采用 CK 和 CK# 两个差分时钟输入，确保精确的时序控制。 6. **8个内部银行**：通过多银行设计，提高并发访问能力，增加数据吞吐量。 7. **片选输出终止(ODT)**：对数据、 strobe 和 mask 信号提供可编程的片选输出终止，以优化信号完整性。 8. **可编程 CAS 读延迟(CL)**：用户可以设置 CAS 读取延迟，以适应不同的系统需求。 9. **可编程后置 CAS 增加延迟(AL)**：允许在 CAS 读取操作后附加延迟。 10. **可编程 CAS 写延迟(CWL)**：写操作的 CAS 延迟也可编程，以优化写入性能。 11. **固定突发长度(BL)**：默认为8，可以通过模式寄存器集(MRS)启用突发切分(BC)功能，设置为4。 12. **可选BC4或BL8**：在运行时可以动态选择突发长度4或8。 13. **自我刷新模式**：在低功耗场景下，内存可以进入自我刷新状态，保持数据完整性。 14. **温度条件下的刷新**：在不同的温度范围内，有不同的刷新周期要求，以保证数据稳定性。 15. **自我刷新温度(SRT)**：根据环境温度自动调整刷新策略。 16. **自动自我刷新(ASR)**：系统可自动触发自我刷新，无需外部控制。 17. **写入校准**：确保数据在写入时的准确对齐。 18. **多功能寄存器**：用于存储和管理各种配置参数。 19. **输出驱动校准**：优化输出驱动器的性能，确保信号质量。此外，产品标记信息提供了关于内存芯片配置的细节，例如512M x 4表示每个芯片有512兆字节（MiB）的数据存储能力，由4条数据线组成。这些特性使得 Micron 的 DDR3L SDRAM 芯片适合于需要低功耗和高性能的系统应用，如笔记本电脑、服务器和嵌入式系统等。

Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally

configured as an 8-bank DRAM.

Figure 3: 512 Meg x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

Address

256

(x32)

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(32,768 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To pullup/pulldown

networks

READ

drivers

DQ[3:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

CK,CK#

DQS, DQS#

ODT

control

ZQ CAL

WE#

RZQ

CK, CK#

RAS#

CAS#

CS#

ODT

CKE

RESET#

CK,CK#

DLL

DQ[3:0]

(1 . . . 4)

(1, 2)

SW1

SW2

DDQ

TT,nom

TT(WR)

SW1

SW2

DDQ

TT,nom

TT(WR)

SW1

SW2

DDQ

TT,nom

TT(WR)

BC4

BC4 (burst chop)

BC4

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

A12

SSQ

OTF

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 4: 256 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

Memory

array

(32,768 x 128 x 64)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

Read

drivers

DQ[7:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

DM/TDQS

(shared pin)

TDQS#

CK, CK#

DQS/DQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

SW1 SW2

DDQ

TT(WR)

TT,nom

SW1 SW2

DDQ

TT,nom

TT(WR)

SW1 SW2

DDQ

TT,nom

TT(WR)

BC4 (burst chop)

BC4

Write

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128

x64)

ODT

control

Address

A12

SSQ

OTF

Figure 5: 128 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

SW1

SW2

DDQ

BC4

SW1

SW2

DDQ

TT,nom

TT(WR)

SW1

SW2

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

DDQ

TT,nom

TT(WR)

TT,nom

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[14:13],

A12/BC#, A11,

A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

DDQ

and DC LOW ≤

0.2 × V

DDQ

. RESET# assertion and deassertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to V

REFDQ

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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