精通FPGA：必备学习资源与设计指南

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"这是一份关于FPGA学习的综合资源，包含了Xilinx公司的9.2i版本Synthesis and Simulation Design Guide。这份文档是为使用Xilinx FPGA进行设计开发的工程师提供的，旨在帮助他们理解和实现FPGA上的设计。" 在FPGA（Field-Programmable Gate Array，现场可编程门阵列）的学习过程中，Synthesis和Simulation是两个至关重要的步骤。Synthesis是指将高级语言（如Verilog或VHDL）编写的硬件描述语言转换为逻辑门级的网表，这个过程涉及到优化，以确保设计能在目标FPGA上高效运行。Simulation则是验证设计功能是否正确的过程，通常在设计实现之前进行，以找出并修复潜在错误。 Xilinx的Synthesis and Simulation Design Guide提供了详细的指导，涵盖了如何有效地进行这两项任务。该文档可能包括以下内容： 1. **基础概念**：解释FPGA的基本结构，如查找表（LUT）、分布式RAM、I/O单元等，以及这些组件如何构成逻辑设计。 2. **流程介绍**：介绍完整的FPGA设计流程，包括设计输入、综合、约束设置、仿真、实现和编程等步骤。 3. **工具使用**：详细描述Xilinx的工具，如Vivado或ISE，如何进行综合和仿真，包括设置参数、优化选项以及报告分析。 4. **设计技巧**：提供优化设计性能和资源利用率的建议，例如逻辑综合策略、时序约束的设定等。 5. **仿真技术**：讲解如何使用ModelSim等仿真器进行功能和时序仿真，确保设计的正确性。 6. **知识产权（IP）集成**：指导如何导入和使用预封装的IP核，如PCIe、DDR内存控制器等。 7. **错误排查**：提供常见问题及解决方法，帮助学习者克服设计过程中遇到的困难。 8. **合规与法律信息**：强调了Xilinx的设计只能用于指定目的，未经授权不得复制或分发，并且使用设计可能需要获得其他权利许可。这份9.2i版本的指南反映了较早的设计工具和流程，但其基本原理和步骤在当前的FPGA设计中仍然适用。虽然Xilinx可能已经更新了工具和版本，但对于初学者来说，了解早期版本可以帮助理解FPGA设计的基本概念和演变历程。在深入学习FPGA时，不仅要掌握理论知识，还需要实践操作来巩固理解。通过实际项目和动手实验，可以更好地应用所学知识，同时也能锻炼解决问题的能力。随着经验的积累，可以逐步接触更复杂的设计和高级特性，如高速接口、并行处理和嵌入式系统集成等。

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9.2i

Choosing Implementation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Choosing Options for Maximum Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Performance Evaluation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Packing and Placement Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Physical Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Xplorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Timing Closure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Best Performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Evaluating Critical Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Understanding Characteristics of Critical Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Many Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Few Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

18 www.xilinx.com Synthesis and Simulation Design Guide

9.2i

Chapter 1: Introduction to Synthesis and Simulation

Advantages of Using Hardware Description Languages

(HDLs) to Design FPGA Devices

FPGA devices are superior to ASIC devices for your design needs. Using Hardware

Description Languages (HDLs) to design high-density FPGA devices has the following

advantages:

• Top-Down Approach for Large Projects

Designers use HDLs to create complex designs. The top-down approach to system

design works well for large HDL projects that require many designers working

together. After the design team determines the overall design plan, individual

designers can work independently on separate code sections.

• Functional Simulation Early in the Design Flow

You can verify design functionality early in the design flow by simulating the HDL

description. Testing your design decisions before the design is implemented at the

early on.

• Synthesis of HDL Code to Gates

Synthesizing your hardware description to target the FPGA implementation:

♦ Decreases design time by allowing a higher-level design specification, rather than

specifying the design from the FPGA base elements.

♦ Reduces the errors that can occur during a manual translation of a hardware

description to a schematic design.

♦ Allows you to apply the automation techniques used by the synthesis tool (such

as machine encoding styles and automatic I/O insertion) during optimization to

the original HDL code. This results in greater optimization and efficiency.

• Early Testing of Various Design Implementations

HDLs allow you to test different design implementations early in the design flow. Use

the synthesis tool to perform the logic synthesis and optimization into gates.

Additionally, Xilinx FPGA devices allow you to implement your design at your

computer. Since the synthesis time is short, you have more time to explore different

architectural possibilities at the Register Transfer Level (RTL). You can reprogram

Xilinx FPGA devices to test several design implementations.

• Reuse of RTL Code

You can retarget RTL code to new FPGA devices with minimum recoding.

Designing FPGA Devices With Hardware Description Languages

(HDLs)

This section discusses Designing FPGA Devices with Hardware Description Languages

(HDLs), and includes:

• “Understanding Hardware Description Languages (HDLs)”

• “Designing FPGA Devices with VHDL”

• “Designing FPGA Devices with Verilog”

• “Designing FPGA Devices with Synthesis Tools”

• “Using FPGA System Features”

Synthesis and Simulation Design Guide www.xilinx.com 19

9.2i

Designing FPGA Devices With Hardware Description Languages (HDLs)

• “Designing Hierarchy”

• “Specifying Speed Requirements”

Understanding Hardware Description Languages (HDLs)

If you are used to schematic design entry, you may find it difficult at first to create

Hardware Description Languages (HDLs) designs. You must make the transition from

graphical concepts, such as block diagrams, state machines, flow diagrams, and truth

tables, to abstract representations of design components. To ease this transition, keep your

overall design plan in mind as you code in HDL.

To effectively use an HDL, you must understand the:

• Syntax of the language

• Synthesis and simulator tools

• Architecture of your target device

• Implementation tools

Designing FPGA Devices with VHDL

VHSIC Hardware Description Language (VHDL) is a hardware description language for

designing integrated circuits. Since VHDL was not originally intended as an input to

synthesis, many VHDL constructs are not supported by synthesis tools. The high level of

abstraction of VHDL makes it easy to describe the system-level components and test

benches that are not synthesized. In addition, the various synthesis tools use different

subsets of VHDL.

The examples in this Guide work with most FPGA synthesis tools. The coding strategies

presented in the remaining chapters of this Guide can help you create Hardware

Description Language (HDL) descriptions that can be synthesized.

Designing FPGA Devices with Verilog

Verilog is popular for synthesis designs because:

• Verilog is less verbose than traditional VHDL.

• Verilog is standardized as IEEE-STD-1364-95 and IEEE-STD-1364-2001.

Since Verilog was not originally intended as an input to synthesis, many Verilog constructs

are not supported by synthesis tools. The Verilog coding examples in this Guide were

tested and synthesized with current, commonly-used FPGA synthesis tools. The coding

strategies presented in the remaining chapters of this Guide can help you create Hardware

Description Language (HDL) descriptions that can be synthesized.

SystemVerilog is a new emerging standard for both synthesis and simulation. It is not

known if, or when, this standard will be adopted and supported by the various design

tools.

Whether or not you plan to use this new standard, Xilinx recommends that you:

• Review the standard to ensure that your current Verilog code can be readily carried

forward as the new standard evolves.

• Review any new keywords specified by the standard.

• Avoid using the new keywords in your current Verilog code.

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9.2i

Chapter 1: Introduction to Synthesis and Simulation

Designing FPGA Devices with Synthesis Tools

Most synthesis tools have special optimization algorithms for Xilinx FPGA devices.

Constraints and compiling options perform differently depending on the target device.

Some commands and constraints in ASIC synthesis tools do not apply to FPGA devices. If

you use them, they may adversely impact your results.

You should understand how your synthesis tool processes designs before you create FPGA

designs. Most FPGA synthesis vendors include information in their documentation

specifically for Xilinx FPGA devices.

Using FPGA System Features

To improve device performance, area utilization, and power characteristics, create

Hardware Description Language (HDL) code that uses FPGA system features such as

DCM, multipliers, shift registers, and memory. For a description of these and other

features, see the device data sheet and user guide. The choice of the size (width and depth)

and functional characteristics must be taken into account by understanding the target

FPGA resources and making the proper system choices to best target the underlying

architecture.

Designing Hierarchy

Hardware Description Languages (HDLs) give added flexibility in describing the design.

Not all HDL code is optimized the same. How and where the functionality is described can

have dramatic effects on end optimization. For example:

• Certain techniques may unnecessarily increase the design size and power while

decreasing performance.

• Other techniques can result in more optimal designs in terms of any or all of those

same metrics.

This Guide will help instruct you in techniques for optional FPGA design methodologies.

Design hierarchy is important in both the implementation of an FPGA and during

interactive changes. Some synthesizers maintain the hierarchical boundaries unless you

group modules together. Modules should have registered outputs so their boundaries are

not an impediment to optimization. Otherwise, modules should be as large as possible

within the limitations of your synthesis tool.

The “5,000 gates per module” rule is no longer valid, and can interfere with optimization.

Check with your synthesis vendor for the preferred module size. As a last resort, use the

grouping commands of your synthesizer, if available. The size and content of the modules

influence synthesis results and design implementation. This Guide describes how to create

effective design hierarchy.

Specifying Speed Requirements

To meet timing requirements, you should understand how to set timing constraints in both

the synthesis tool and the placement and routing tool. If you specify the desired timing at

the beginning, the tools can maximize not only performance, but also area, power, and tool

runtime. This usually results in a design that better matches the desired performance. It

may also result in a design that is smaller, and which consumes less power and requires

less time processing in the tools. For more information, see “Setting Constraints.”

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