Intel® 64 and IA-32 Architectures System Programming Guide, Part 2

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"Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B，系统编程指南第二部分" Intel® 64和IA-32架构软件开发人员手册是针对Intel处理器架构的全面参考资料，由五卷组成。这五卷包括：基础架构、指令集参考A-M、指令集参考N-Z、系统编程指南第一部分以及我们讨论的系统编程指南第二部分。每个部分都专注于特定主题，以帮助开发者充分利用Intel平台进行系统级编程。 Volume 3B——系统编程指南第二部分，主要关注的是操作系统和系统程序员需要了解的高级特性、硬件接口以及系统管理。以下是一些关键知识点： 1. **虚拟化技术**：涵盖Intel的硬件虚拟化技术，如VT-x（Intel Virtualization Technology）和EPT（Extended Page Tables），这些技术增强了在单个物理硬件上运行多个虚拟机的能力。 2. **内存管理**：详细介绍了Intel 64和IA-32架构中的内存模型，包括分页机制、页表结构、内存保护和内存映射。 3. **中断和异常处理**：文档详细描述了中断、异常和系统调用的处理流程，这对于编写内核级代码至关重要。 4. **处理器性能监控**：涵盖了使用性能监视单元（Performance Monitoring Unit, PMU）来收集和分析处理器性能数据的方法。 5. **电源管理和ACPI**：解释了如何利用硬件提供的电源管理功能，包括C状态（C-states）和PCI Express的低功耗状态。此外，还介绍了Advanced Configuration and Power Interface（ACPI）规范，用于操作系统控制系统的电源状态。 6. **多处理器系统**：对于开发多处理器（SMP）系统，手册详细说明了MP配置、总线协议和多处理器同步。 7. **系统初始化和POST**：阐述了系统启动过程，包括基本输入/输出系统（BIOS）和固件接口的早期阶段。 8. **设备驱动程序开发**：介绍与硬件设备交互所需的编程接口，包括中断处理和I/O端口访问。 9. **系统安全和防护**：讨论了防止恶意软件攻击的安全特性，如执行禁用位（DEP）、数据执行防护（DEP）和地址空间布局随机化（ASLR）。 10. **调试工具和接口**：描述了内建的调试器支持，如调试端口、调试寄存器和调试事件。这个手册是软件开发人员、系统管理员和硬件工程师的重要参考资料，因为它提供了深入的硬件细节，有助于优化性能、调试问题并确保系统稳定性和兼容性。由于Intel产品持续发展，因此开发者应根据具体版本更新信息，确保掌握最新的硬件特性和功能。

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VIRTUAL-MACHINE CONTROL STRUCTURES

—2: Shutdown. The logical processor is inactive because it incurred a triple

fault

or some other serious error.

—3: Wait-for-SIPI. The logical processor is inactive because it is waiting for a

startup-IPI (SIPI).

Future processors may include support for other activity states. Software should

read the VMX capability MSR IA32_VMX_MISC (see Appendix G.6) to determine

what activity states are supported.

• Interruptibility state (32 bits). The IA-32 architecture includes features that

permit certain events to be blocked for a period of time. This field contains

information about such blocking. Details and the format of this field are given in

Table 21-3.

1. A triple fault occurs when a logical processor encounters an exception while attempting to

deliver a double fault.

Table 21-3. Format of Interruptibility State

Bit

Position(s)

Bit Name Notes

0 Blocking by STI See the “STI—Set Interrupt Flag” section in Chapter 4 of the

Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 2B.

Execution of STI with RFLAGS.IF = 0 blocks interrupts (and,

optionally, other events) for one instruction after its

execution. Setting this bit indicates that this blocking is in

effect.

1Blocking by

MOV SS

See the “MOV—Move a Value from the Stack” and “POP—Pop

a Value from the Stack” sections in Chapter 3 and Chapter 4

of the Intel® 64 and IA-32 Architectures Software

Developer’s Manual, Volumes 2A & 2B, and Section 6.8.3 in

the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A.

Execution of a MOV to SS or a POP to SS blocks interrupts for

one instruction after its execution. In addition, certain debug

exceptions are inhibited between a MOV to SS or a POP to SS

and a subsequent instruction. Setting this bit indicates that

the blocking of all these events is in effect. This document

uses the term “blocking by MOV SS,” but it applies equally to

POP SS.

2 Blocking by SMI See Section 26.2. System-management interrupts (SMIs) are

disabled while the processor is in system-management mode

(SMM). Setting this bit indicates that blocking of SMIs is in

effect.

Vol. 3 21-9

VIRTUAL-MACHINE CONTROL STRUCTURES

• Pending debug exceptions (64 bits; 32 bits on processors that do not support

Intel 64 architecture). IA-32 processors may recognize one or more debug

exceptions without immediately delivering them.

This field contains information

about such exceptions. This field is described in Table 21-4.

3 Blocking by NMI See Section 6.7.1 in the Intel® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 3A and Section 26.8.

Delivery of a non-maskable interrupt (NMI) or a system-

management interrupt (SMI) blocks subsequent NMIs until

the next execution of IRET. See Section 22.4 for how this

behavior of IRET may change in VMX non-root operation.

Setting this bit indicates that blocking of NMIs is in effect.

Clearing this bit does not imply that NMIs are not

(temporarily) blocked for other reasons.

If the “virtual NMIs” VM-execution control (see Section

21.6.1) is 1, this bit does not control the blocking of NMIs.

Instead, it refers to “virtual-NMI blocking” (the fact that guest

software is not ready for an NMI).

31:4 Reserved VM entry will fail if these bits are not 0. See Section 23.3.1.5.

1. For example, execution of a MOV to SS or a POP to SS may inhibit some debug exceptions for one

instruction. See Section 6.8.3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 3A. In addition, certain events incident to an instruction (for example, an INIT signal) may

take priority over debug traps generated by that instruction. See Table 6-2 in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Table 21-4. Format of Pending-Debug-Exceptions

Bit

Position(s)

Bit Name Notes

3:0 B3 – B0 When set, each of these bits indicates that the corresponding

breakpoint condition was met. Any of these bits may be set

even if the corresponding enabling bit in DR7 is not set.

11:4 Reserved VM entry fails if these bits are not 0. See Section 23.3.1.5.

12 Enabled

breakpoint

When set, this bit indicates that at least one data or I/O

breakpoint was met and was enabled in DR7.

Table 21-3. Format of Interruptibility State (Contd.)

Bit

Position(s)

Bit Name Notes

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VIRTUAL-MACHINE CONTROL STRUCTURES

• VMCS link pointer (64 bits). This field is included for future expansion. Software

should set this field to FFFFFFFF_FFFFFFFFH to avoid VM-entry failures (see

Section 23.3.1.5).

• VMX-preemption timer value (32 bits). This field is supported only on logical

processors that support the 1-setting of the “activate VMX-preemption timer”

VM-execution control. This field contains the value that the VMX-preemption

timer will use following the next VM entry with that setting. See Section 22.7.1

and Section 23.6.4.

• Page-directory-pointer-table entries (PDPTEs; 64 bits each). These four (4)

fields (PDPTE0, PDPTE1, PDPTE2, and PDPTE3) are supported only on logical

processors that support the 1-setting of the “enable EPT” VM-execution control.

They correspond to the PDPTEs referenced by CR3 when PAE paging is in use (see

Section 4.4 in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A). They are used only if the “enable EPT” VM-execution control

is 1.

21.5 HOST-STATE AREA

This section describes fields contained in the host-state area of the VMCS. As noted

earlier, processor state is loaded from these fields on every VM exit (see Section

24.5).

All fields in the host-state area correspond to processor registers:

• CR0, CR3, and CR4 (64 bits each; 32 bits on processors that do not support Intel

64 architecture).

• RSP and RIP (64 bits each; 32 bits on processors that do not support Intel 64

architecture).

• Selector fields (16 bits each) for the segment registers CS, SS, DS, ES, FS, GS,

and TR. There is no field in the host-state area for the LDTR selector.

• Base-address fields for FS, GS, TR, GDTR, and IDTR (64 bits each; 32 bits on

processors that do not support Intel 64 architecture).

13 Reserved VM entry fails if this bit is not 0. See Section 23.3.1.5.

14 BS When set, this bit indicates that a debug exception would

have been triggered by single-step execution mode.

63:15 Reserved VM entry fails if these bits are not 0. See Section 23.3.1.5.

Bits 63:32 exist only on processors that support Intel 64

architecture.

Table 21-4. Format of Pending-Debug-Exceptions (Contd.)

Bit

Position(s)

Bit Name Notes

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VIRTUAL-MACHINE CONTROL STRUCTURES

All other bits in this field are reserved, some to 0 and some to 1. Software should

consult the VMX capability MSRs IA32_VMX_PINBASED_CTLS and

IA32_VMX_TRUE_PINBASED_CTLS (see Appendix G.3.1) to determine how to set

reserved bits. Failure to set reserved bits properly causes subsequent VM entries to

fail (see Section 23.2).

The first processors to support the virtual-machine extensions supported only the 1-

settings of bits 1, 2, and 4. The VMX capability MSR IA32_VMX_PINBASED_CTLS will

always report that these bits must be 1. Logical processors that support the 0-

settings of any of these bits will support the VMX capability MSR

IA32_VMX_TRUE_PINBASED_CTLS MSR, and software should consult this MSR to

discover support for the 0-settings of these bits. Software that is not aware of the

functionality of any one of these bits should set that bit to 1.

21.6.2 Processor-Based VM-Execution Controls

The processor-based VM-execution controls constitute two 32-bit vectors that

govern the handling of synchronous events, mainly those caused by the execution of

specific instructions.

These are the primary processor-based VM-execution

controls and the secondary processor-based VM-execution controls.

Table 21-5. Definitions of Pin-Based VM-Execution Controls

Bit Position(s) Name Description

0External-interrupt

exiting

If this control is 1, external interrupts cause VM exits.

Otherwise, they are delivered normally through the guest

interrupt-descriptor table (IDT). If this control is 1, the value

of RFLAGS.IF does not affect interrupt blocking.

3 NMI exiting If this control is 1, non-maskable interrupts (NMIs) cause

VM exits. Otherwise, they are delivered normally using

descriptor 2 of the IDT. This control also determines

interactions between IRET and blocking by NMI (see Section

22.4).

5 Virtual NMIs If this control is 1, NMIs are never blocked and the “blocking

by NMI” bit (bit 3) in the interruptibility-state field indicates

“virtual-NMI blocking” (see Table 21-3). This control also

interacts with the “NMI-window exiting” VM-execution

control (see Section 21.6.2).

This control can be set only if the “NMI exiting” VM-execution

control (above) is 1.

6Activate VMX-

preemption timer

If this control is 1, the VMX-preemption timer counts down in

VMX non-root operation; see Section 22.7.1. A VM exit occurs

when the timer counts down to zero; see Section 22.3.

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