A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in
0.18
μ
m CMOS
Yuhua Liang, Zhangming Zhu
*
School of Microelectronics, Xidian University, Xi'an, 710071, China
ARTICLE INFO
Keywords:
SAR ADC
Low power
Switching scheme
ABSTRACT
This paper presents a 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor
switching strategy in 0.18
μ
m CMOS process. The SAR ADC with this proposed strategy features better linearity
due to the use of a relatively lower assistant reference, the value of which is equivalent to a quarter of the input
swing. In addition, the accuracy of the assistant reference has no impact on the ADC performance, since only this
assistant reference will be involved with the capacitive DACs during the conversion period. The ADC is powered
by the supplies of 0.6 V/0.15 V. The capacitive DACs are supplied by the 0.15 V assistant reference, while the
other blocks are powered by the 0.6 V reference. In this case, the ADC consumes 11.7 nW overall, resulting in a
figure-of-merit (FOM) of 1.6fJ/conversion-step. At a 20-kS/s output rate, the measured results show the proposed
SAR ADC performs a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB, a peak spurious-free-dynamic-
range (SFDR) of 66.7 dB. The core area of the designed ADC is and 370 310
μ
m
2
.
1. Introduction
Owing to the advantages of simple structure, minimal usage of analog
block and energy-efficiency, SAR ADCs are the optimal choice in many
low-power application areas. Moreover, SAR ADCs feature high
compatibility with the increasingly scaling-down semiconductor
manufacturing process and can work at low supply voltages. These ad-
vantages endow SAR ADCs with the possibility to become a trend as the
semiconductor manufacturing process develops.
Among the function blocks in an SAR ADC, the capacitive DACs are
always a major contributor to the power consumption. And the employed
switching strategy is a major factor of the power consumed by the
capacitive DACs.
During the past several years, researchers all over the world
endeavored themselves to improve the power efficiency of the SAR ADCs
with efficient switching schemes [1–7]. It is noted that the effectiveness
of the schemes in Refs. [6,7] are inferior to that of what proposed in
Ref. [5]. Compared with the scheme proposed in Ref. [ 5], the switching
energy of the proposed scheme can be reduced by 51% approximately.
When the reset energy is taken into consideration, a reduction of 83.4% is
achieved in total.
It is known that the linearity of the SAR ADC depends on both the
matching property of the DACs and the employed switching strategy.
Thanks to the utilization of 1/4Vref (rather than Vcm ¼ 1/2Vref or Vref)
in the conversion period, the linearity of an SAR ADC that adopts the
proposed approach can be improved significantly. On condition of the
same unit capacitor, the standard deviation of the maximum differential-
non-linearity (DNL) for the proposed strategy can be reduced to a quarter
of that for the set-and-down strategy.
Observing the quantization process of the Vcm-involved strategies
[2–5], we arrive at the conclusion that any mismatch between Vcm and
Vref can degrade the ADC performance. Provided that the proposed
strategy is employed, only the assistant reference 1/4Vref will be
involved in the conversion course. Therefore, not only can the power
efficiency be improved, but also the ADC performance is immune to the
inaccuracy of the assistant reference.
To verify the advantages of the proposed switching strategy, a 10bit
0.6Vpp 20 kS/s SAR ADC is fabricated in 0.18
μ
m CMOS technology. The
capacitive DACs are powered by the 0.15 V assistant reference, which is a
quarter of the swing of the inputs. Detailed descriptions and discussions
will be given in the following sections.
2. Architecture design
The diagram of the proposed SAR ADC is shown in Fig. 1.Itis
composed of two differential binary-weighted capacitive DACs, two
* Corresponding author.
E-mail address: zhangmingzhu@xidian.edu.cn (Z. Zhu).
Contents lists available at ScienceDirect
Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo
https://doi.org/10.1016/j.mejo.2018.01.006
Received 4 January 2017; Received in revised form 7 November 2017; Accepted 8 January 2018
Available online 3 February 2018
0026-2692/© 2018 Elsevier Ltd. All rights reserved.
Microelectronics Journal 73 (2018) 24–29
下载后可阅读完整内容，剩余5页未读，立即下载
weixin_38696090
- 粉丝: 4
- 资源: 874
我的内容管理
展开
最新资源
- 深入理解23种设计模式
- 制作与调试：声控开关电路详解
- 腾讯2008年软件开发笔试题解析
- WebService开发指南：从入门到精通
- 栈数据结构实现的密码设置算法
- 提升逻辑与英语能力：揭秘IBM笔试核心词汇及题型
- SOPC技术探索：理论与实践
- 计算图中节点介数中心性的函数
- 电子元器件详解：电阻、电容、电感与传感器
- MIT经典：统计自然语言处理基础
- CMD命令大全详解与实用指南
- 数据结构复习重点：逻辑结构与存储结构
- ACM算法必读书籍推荐：权威指南与实战解析
- Ubuntu命令行与终端：从Shell到rxvt-unicode
- 深入理解VC_MFC编程：窗口、类、消息处理与绘图
- AT89S52单片机实现的温湿度智能检测与控制系统
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
