STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3编程手册

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"STM32F10xxx20xxx21xxxL1xxxx Cortex-M3 编程手册" 本文档是STM32F10xxx、20xxx、21xxx以及L1xxxx系列微控制器的Cortex-M3编程手册，主要面向应用级和系统级软件开发者，详细介绍了处理器的编程模型、指令集以及核心外围设备。 STM32F10xxx/20xxx/21xxx/L1xxxx系列的Cortex-M3处理器是专为微控制器市场设计的一款高性能32位处理器，其主要特性包括： 1. 出色的处理性能：结合快速中断处理能力，能高效应对各种任务需求。 2. 强大的系统调试功能：具备广泛的断点和跟踪能力，简化了调试过程。 3. 效率优化的处理器核心、系统结构和内存管理：保证了程序运行的高效性。 4. 超低功耗：内置的睡眠模式有助于在不影响性能的前提下降低功耗。 5. 平台安全：提供安全保障，增强了系统的稳定性与可靠性。手册内容包含但不限于： 1. 关于文档的信息：这部分介绍文档的排版约定、寄存器缩写的列表，以及关于STM32 Cortex-M3处理器和核心外围设备的概述。 2. Cortex-M3处理器和核心外围设备：深入讲解处理器的体系结构，包括系统层面的细节。 3. 指令集：详述Cortex-M3支持的指令，帮助开发者理解如何编写高效的代码。 4. 外围设备接口：介绍STM32F10xxx/20xxx/21xxx/L1xxxx系列的外设，如GPIO、定时器、串口等，及其使用方法。 5. 存储器映射：描述了处理器如何访问和操作不同的内存区域。 6. 特性描述：包括电源管理、中断和异常处理、调试接口等。 7. 应用示例和最佳实践：提供了实际应用中的代码示例和建议，以帮助开发者更好地利用处理器的特性。 8. 错误处理和异常：解释了如何处理运行时可能出现的错误和异常情况。 9. 开发工具和软件支持：讨论了适用于STM32的开发环境、IDE、编译器和库，以及如何集成它们进行项目开发。 10. 低功耗模式：详细阐述了各种低功耗模式的配置和切换，以实现最优的能效比。 11. 安全性和固件升级：介绍了如何确保代码的安全性以及固件的更新机制。通过这份编程手册，开发者可以全面了解STM32F10xxx/20xxx/21xxx/L1xxxx系列微控制器的特性和使用方法，从而有效地进行嵌入式系统的设计和开发工作。此外，手册还提供了大量的参考资料，如参考手册、数据手册和技术支持网站（www.st.com），以便开发者获取更多实时更新的信息和资料。

The Cortex

-M3 processor PM0056

16/156 DocID15491 Rev 6

Program status register

The Program Status Register (PSR) combines:

• Application Program Status Register (APSR)

• Interrupt Program Status Register (IPSR)

• Execution Program Status Register (EPSR)

These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are

as shown in

Figure 3 and Figure 4.

Figure 3. APSR, IPSR and EPSR bit assignments

Figure 4. PSR bit assignments

Access these registers individually or as a combination of any two or all three registers,

using the register name as an argument to the MSR or MRS instructions. For example:

• Read all of the registers using PSR with the MRS instruction

• Write to the APSR using APSR with the MSR instruction.

The PSR combinations and attributes are:

See the instruction descriptions MRS on page 100 and MSR on page 101 for more

information about how to access the program status registers.

Table 3. PSR register combinations

PSR read-write

(1), (2)

1. The processor ignores writes to the IPSR bits.

2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits

APSR, EPSR, and IPSR

IEPSR read-only EPSR and IPSR

IAPSR read-write

(1)

APSR and IPSR

EAPSR read-write

(2)

APSR and EPSR

25 24 23

Reserved ISR_NUMBER

31 30 29 28 27

NZCV

Reserved

APSR

IPSR

EPSR

Reserved Reserved

26 16 15 10 9

ReservedICI/IT ICI/ITT

MS48365V1

31 30 29 28 27 26 25 24 23 16 15 10 9 8 0

Z C V Q ICI/IT T Reserved ICI/IT ISR_NUMBER

Reserved

MS48366V1

DocID15491 Rev 6 19/156

PM0056 The Cortex

-M3 processor

155

Execution program status register

The EPSR contains the Thumb state bit, and the execution state bits for either the:

• If-Then (IT) instruction

• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store

multiple instruction.

See the register summary in Table 2 on page 15 for the EPSR attributes. The bit

assignments are:

Attempts to read the EPSR directly through application software using the MSR instruction

always return zero. Attempts to write the EPSR using the MSR instruction in application

software are ignored. Fault handlers can examine EPSR value in the stacked PSR to

indicate the operation that is at fault. See

Section 2.3.7: Exception entry and return on

page 37

Interruptible-continuable instructions

When an interrupt occurs during the execution of an LDM or STM instruction, the processor:

• Stops the load multiple or store multiple instruction operation temporarily

• Stores the next register operand in the multiple operation to EPSR bits[15:12].

After servicing the interrupt, the processor:

• Returns to the register pointed to by bits[15:12]

• Resumes execution of the multiple load or store instruction.

When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

If-Then block

The If-Then block contains up to four instructions following a 16-bit IT instruction. Each

instruction in the block is conditional. The conditions for the instructions are either all the

same, or some can be the inverse of others. See

IT on page 94 for more information.

Exception mask registers

The exception mask registers disable the handling of exceptions by the processor. Disable

exceptions where they might impact on timing critical tasks.

Table 6. EPSR bit definitions

Bits Description

Bits 31:27 Reserved.

Bits 26:25, 15:10 ICI: Interruptible-continuable instruction bits

See Interruptible-continuable instructions on page 19.

Bits 26:25, 15:10 IT: Indicates the execution state bits of the IT instruction, see

IT on page 94.

Bit 24 Always set to 1.

Bits 23:16 Reserved.

Bits 9:0] Reserved.

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