Spartan6 PLL ADV程序：解决Xilinx时钟错误的解决方案

//-----------------------------------------------------------------------------
//-- $Id: LED.v, v 0.1 2012/06/28 10:28:54 Aku
//------------------------------------------------------------------------------
//-- Title         : Siga-S16 Verilog Examble
//-- File          : LED.v
//-- Project       : Siga-S16
//-- Author        : Aku  <sigadsp@126.com>
//-- Created       : 4.7.2012
//------------------------------------------------------------------------------
//-- Description   : Siga-S16 led example 
//------------------------------------------------------------------------------
//-- History       : 
//------------------------------------------------------------------------------
//-- Copyright (C) SigaDSP
//-- All rights reserved. Reproduction in whole or part is prohibited 
//-- without a written permission of the copyright owner.
//------------------------------------------------------------------------------


`timescale 1ns / 1ps


module led (
               // inputs:
                  clk,
                  rst,
                  timer,
clk_2x_0_o,
clk_2x_180_o,
 clk0_bufg_in_o,

 mcb_drp_clk_bufg_in_o,
 sd_clk_o,
 vga_clk_o
             );
 
//===========================================================================
// PORT declarations
//===========================================================================
input clk;
input rst;
output reg timer;
output    clk_2x_0_o;
output     clk_2x_180_o;
output     clk0_bufg_in_o;
output     mcb_drp_clk_bufg_in_o;
output  sd_clk_o;
output  vga_clk_o;
  wire                       clkfbout_clkfbin;
  wire                       locked;

//  wire  clk0_bufg_in_i;
//  wire mcb_drp_clk_bufg_in_i;
//  wire sd_clk_o;
 wire vga_clk_i;
  always @(posedge clk or posedge rst)
    begin
      if (rst)
          timer <= 0;
      else
          timer <=!timer;