高性能ASIC设计：多米诺逻辑在ASIC流程中的应用

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"《High Performance ASIC Design_ Using Synthesizable Domino Logic in an ASIC Flow》是针对高级ASIC设计的一本实践性书籍，主要介绍了如何在ASIC设计流程中利用可综合的多米诺逻辑来实现高性能。本书由具有多年工业经验的作者Razak Hossain撰写，适合ASIC底层开发者阅读。" 在ASIC（Application-Specific Integrated Circuit）设计领域，追求高性能是至关重要的，而多米诺逻辑由于其高速特性，被广泛用于提高电路的运行速度。本书首先提供了一个关于如何在ASIC设计中实现高速性能的概述，涵盖了各种设计技术。接着，书中详细阐述了多米诺逻辑标准单元库的设计和表征过程，以及先进的多米诺逻辑综合流程。多米诺逻辑是一种高速互补金属氧化物半导体（CMOS）逻辑风格，它的主要特点是消除传统静态逻辑中的门延迟，通过快速的电荷翻转来加速信号传递。书中详细介绍了如何在自动化框架下有效地使用这种逻辑，并通过实际的硅测量结果验证了所采用方法的可行性。这些结果证明了多米诺逻辑在提高电路速度方面的能力。除了理论讲解，书中还包含了一系列实际设计示例，如微处理器执行单元的实现和维特比解码器的设计。这些例子让读者能够了解如何将这些技术应用于真实的工程实践中。对于研究生、电子和计算机工程的研究人员，以及工业界的电路设计师和EDA（Electronic Design Automation）工程师来说，这本书是一个宝贵的参考资料。 Razak Hossain作为意法半导体公司的首席资深工程师，他的专业知识和实践经验使得这本书的内容更加权威和实用。读者可以通过这本书深入理解多米诺逻辑在ASIC设计中的应用，提升自己在高速电路设计领域的专业技能。

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4 High Performance ASIC Design

company in the world, with its semiconductor revenues far exceeding that of IBM itself.

The rest, as they say, is history.

As semiconductor manufacturing progressed, the largest challenge to the nascent

industry was the ability to design and verify designs using the increasing number of

transistors available. This need was met by the development of a new ﬁeld of soft-

ware, often closely tied to dedicated hardware in its early years, called electronic design

automation (EDA). EDA developments started in the 1960s, with software developed

in-house by different semiconductor companies. In the early years of EDA the most

common tools developed were circuit and logic simulators, which allowed designers to

verifythe expected functionality of a design before manufacturing. Alberto Sangiovanni-

Vincentelli states in his excellent history of EDA (The Tides of EDA) that the early tools

had limited loyalty due to the perceived limited value-added of the tools [7]. By the

late 1980s continued developments in EDA had resulted in the development of logic

synthesis, which could map a register transfer level (RTL) description to a set of stan-

dard cell gates and memory instances, and automated physical design tools, which could

physically instantiate and route the wires needed to complete the physical design. These

tools led to a marked improvement in productivity, allowing digital designs to be quickly

implemented based on a higher abstraction level, behavioral RTL description [7]. The

increasing complexity of EDA tools, along with the realization of their tremendous

usefulness, led to the rise of independent EDA companies and a rapid reduction in EDA

tool development within semiconductor companies. By the end of 2006, the EDA indus-

try had a total available market (TAM) of 5.3 billion dollars [8], which is about 2% of

the worldwide semiconductor TAM of 260 billion dollars [9]. The success of CMOS

manufacturing technology, along with the availability of powerful EDA tools, allowed

for the widespread penetration of electronics into a multitude of applications.

People who are drawninto, and ultimately stay in, engineering are generally somewhat

private people. Our work must, by deﬁnition, be cooperative, but the bread and butter of

our daily tasks tends to be very solitary exercises. I am aware that such an audience feels

extremely uncomfortable with broad, historical utterances, reminding them of overly

optimistic forecasts they have had to sit through in darkened conference rooms with a

roll of the eye and a quick, knowingsmile to a colleague. Still, I feel compelled to state the

following:Ihaveno doubt that lookingback fromthe future,the most important historical

event of our age will be the development and promulgation of digital technology. It will

also be seen as a profoundly positive development. I believe that all of us working in

this ﬁeld should be proud of our achievements. I have said my piece and now return to

the theme of digital ASIC design.

It may have been assumed that the emergence of ASIC design methodologies would

displace all other techniques for implementing digital CMOS logic. This has not hap-

pened, as many digital designs have speciﬁc needs that cannot be achieved by using

standard ASIC techniques. In recent years the capabilities of ASIC tools have increased

greatly, largely due to the tremendous competition among the companies in the ﬁeld.

Many logical and behavioral optimizations that previously had to be hand-coded for efﬁ-

cient implementation are now automatically incorporated in the synthesis tools. The two

most common beneﬁts of custom design are its ability to optimize across the different

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6 High Performance ASIC Design

The AND gate shown in Figure 1.3 can be used to illustrate the functionality, the

speed advantage, and also some of the challenges involved in using this logic family. In

Figure 1.3 it can be seen that the two functional inputs, A and B, are also attended by the

clock signal, Clk. At ﬁrst glance this may seem strange, since an AND gate should be

a purely combinational circuit, which unlike latches and ﬂip-ﬂops does not require the

presence of the clock signal. Domino logic is, however, a clocked logic family, which

means that every single logic gate has a clock signal present. When the clock signal

turns low, node N0 (which is called the evaluation or internal node – some authors refer

to it as the dynamic node) goes high, causing the output of the gate to go low. This

represents the only mechanism for the gate output to go low once it has been driven high.

The operating period of the cell when its input clock and output are low is called the

precharge phase or cycle. The next phase, when the clock is high, is called the evaluate

phase or cycle. During the evaluate phase the output of the domino AND cell can go high

provided that both inputs A and B are high, which causes the evaluation node, N0, to be

driven to a low value. The evaluate phase is the functional operating phase in domino

cells, with the precharge phase enabling the next evaluate phase to occur. The appropriate

application of the clock signal ensures that the critical path in domino cells only traverses

through cells in the evaluate phase. One of the advantages of domino logic over static

logic can also be garnered from the schematic in Figure 1.3. Since the domino cell only

switches from a low to a high direction, there is no need for the inputs A and B to drive

any pull-up PMOS transistors. The lack of a PMOS transistor means that the effective

transistor width that loads down a previous stage of logic, for a particular current drive,

favors domino over static logic. This is critical since the key to high speed is ensuring

that a speed advantage can be gained without loading down the cell greatly [10]. For

example, if a design is constructed with a set of cells with transistors of a certain size,

replacing the transistors in every cell with ones ten times larger will almost certainly lead

to a design that is faster. Provided that the initial design is properly sized, i.e., without

weak cells which have very long rise or fall times, the new design will not, however, be

ten times faster. The reason for this is that, while the drive strengths of each cell have

increased by a factor of 10, the output loading due to the input transistor capacitance

seen by each cell has also increased by approximately a factor of 10. Since larger cells

are now used in the design, its area will be larger, leading to greater wiring capacitance.

Thus, while speed gains can be achieved by optimizing cell drives, the indiscriminate

increase in drive strengths tends to limit the improvement in speed due to the increased

self-loading.

In order to see how domino logic alters the relationship between input capacitance and

output drive strength, compared with an equivalent static cell, the reader is directed to

Figure 1.4.Astatic buffer is shown in the ﬁgure, with input PMOS and NMOS transistor

widths of 2 µm and 1 µm, respectively. Assuming that the gate capacitance of a PMOS

and NMOS transistor is the same per unit micrometer of transistor width, the total load

seen by the cell driving the buffer is 3 µmoftransistor gate width. For a domino cell it

is possible to construct a buffer with the same drive strength but which has only 1 µm

of transistor width as input capacitance. Alternately, with the same input capacitance

it is possible to build a stronger and faster domino buffer. This is shown in Figure 1.4,

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8 High Performance ASIC Design

cell has 50% greater drive strength. Thus, for the same input capacitance a domino cell

can result in greater output drive strength than a static equivalent.

There are a few points to note. Firstly, the degradation in drive strength due to the

addition of the footer transistor in a domino buffer is worse than in other domino cells

with more than two NMOS transistors in series. For example, in a three-input domino

AND cell, the number of NMOS transistors in series goes from three to four when

the footed transistor is considered. This is much better than a domino buffer where a

doubling in the height of the NMOS series stack occurs. Secondly, the PMOS pull-up

transistor for the domino cell in Figure 1.4 is shown as 1 µm. The actual size of the

PMOS transistor will depend on the time available for the output of the domino cell to

turn low when the clock falls. This delay is called the precharge delay. In general, the

PMOS pull-up transistor is smaller in a domino cell than the static equivalent. Thirdly,

the ratio of PMOS to NMOS transistor width for the static cell is given as 2. In Chapter 3

we will see that the actual ratios tend to be lower in static logic. Finally, for stability

purposes domino cells tend to use weak feedback keepers placed between the output

and the evaluation node driving the output. For simplicity, that circuit is not shown in

Figure 1.4.

In addition to being able to achieve better output drive strength for input loading,

domino cells also have a speed advantage as they avoid contention when the cells switch.

In order to understand this, one must note that the input to a static cell drives both PMOS

and NMOS transistors. Any input transition that causes the cell to switch logical states

results in a PMOS transistor being turned off and an NMOS transistor being turned on,

or vice versa. Since the inputs to the cell have ﬁnite rise and fall times, this means that

duringthe transition periodboth the PMOSand theNMOStransistors areweakly on. This

contention between the two transistors increases the input voltage level at which the cell

switches. It is possible to speed up the rise or fall transition of a static cell by increasing

or decreasing the ratio of the PMOS to NMOS transistor size. This, however, leads to

the alternate transition becoming slower. Since both transitions are equally important

in static cells, it is difﬁcult to gain very much by skewing a particular transition. For

this reason, the switching point of most static cells tends to be close to half the supply

voltage level (Vdd). For domino cells only the rising transition is critical. If an input rise

causes the evaluation node of the domino cell to discharge, no contention exists between

PMOS and NMOS transistors. This allows domino cells to start switching when the input

voltage level reaches an NMOS transistor threshold voltage level. Figure 1.5 illustrates

the switching behavior of a static and a domino buffer as the data input to the cell rises.

The lower switching voltage of a domino cell leads to a speedup since the input driving

cells will reach the lower NMOS threshold voltage quicker than a higher voltage level.

These factors lead to domino cells being signiﬁcantly faster than equivalent static cells.

The speed advantage of a domino cell over an equivalent static design is in the range of

1.5× to 2.5×.

Domino logic is an uninverting style of logic [11]. This follows since every domino

cell is a single-stage dynamic cell followed by an inverter. Consequently, the only valid

transitions at the output of the gate during the evaluate phase are from a low to a high

value. The uninverting nature of the logic means that while AND gates, OR gates, and

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