SiI9134HDMI Deep Color Transmitter Data Sheet: Confidential SiliconImage Technology

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本文档是关于Silicon Image公司生产的SiI9134 HDMI Deep Color Transmitter的详细数据手册（DS）。SiI9134是一款专为HDMI传输深度颜色信号设计的芯片，它在2010年7月更新，带有版权声明，指出该文档中的所有信息均为专有和机密，包括专利技术、版权和商业秘密。文档标记为SiI-DS-0193-F，适用于Co-Edifice Video Technology内部使用。该数据手册提供了以下关键知识点： 1. **芯片概述**：SiI9134是一款HDMI发射器，特别设计用于处理高带宽的彩色视频信号，支持Deep Color（深度颜色）技术，这在高清电视和多媒体设备中是至关重要的组成部分，能够提供更丰富的色彩表现力。 2. **功能特性**：文档详细列出了芯片的功能特性，如支持不同视频格式、传输速率、带宽管理、时钟同步以及错误检测和纠正机制等，确保了高质量的视频传输性能。 3. **接口与规格**：包含了接口规范，例如HDMI版本兼容性、电源需求、引脚配置和封装类型，这对于硬件工程师在设计系统时选择或集成该芯片非常有用。 4. **安全与保密**：强调了阅读和使用这份文档的条件限制，仅限于非商业目的的评估购买决定，并且只能在购买Silicon Image或其附属公司的产品和服务时，且遵循特定条款和条件。 5. **版权信息**：文档的版权属于Silicon Image, Inc.，任何未经授权的复制、修改、分发或公开展示都是违法的，这体现了知识产权保护的重要性。 6. **日期与版本**：最后修订日期为2010年4月11日，标明了文档的时效性，可能反映了当时的技术标准和市场环境。对于电子工程领域或者需要利用SiI9134进行系统设计的专业人员来说，这份数据手册是必不可少的参考资料，它提供了深入理解芯片工作原理、性能参数以及合规使用的宝贵信息。

Silicon Image

Confidential

for

Co-Edifice Video

Technology

Internal Use Only

SiI9134 HDMI Deep Color Transmitter

Data Sheet

Silicon Image, Inc.

CONFIDENTIAL

Description

The SiI9134 transmitter provides a complete solution for transmitting HDMI digital audio or video. Specialized audio

and video processing available within the transmitter adds HDMI capability to consumer electronics devices easily and

cost effectively. Figure 3 shows t

he functional blocks of the device. Pin descriptions begin on page 25.

Figure 3 Functional Block Diagram

Silicon Image

Confidential

for

Co-Edifice Video

Technology

Internal Use Only

SiI9134 HDMI Deep Color Transmitter

Data Sheet

Silicon Image, Inc.

CONFIDENTIAL

Video Data Input and Conversion

Video Processing Pipeline

Figure 4 shows the video data processing stages. Each of the processing blocks can be bypassed by setting the

appropriate register bits. The HSYNC and VSYNC input signals are required except in embedded sync modes. The DE

input signal is optional; the DE generator can create this signal using the HSYNC and VSYNC pulses.

Figure 4. Transmitter Video Data Processing Path

Input Clock Multiplier/Divider

The input pixel clock can be multiplied by 0.5, 1, 2, or 4. Video input formats that use a 2x clock (such as YC Mux

mode) can then be transmitted across the HDMI link with a 1x clock; similarly with 1x to 2x, 1x to 4x and 2x to 4x.

Video Data Capture Logic

The video data capture logic receives uncompressed digital video through an 8-bit to-24 bit wide interface. The three

8/10/12-bit data channels of the interface can be configured for 17 different video formats (see Table 2 on page 6). It

provides a direct connection to m

ajor A/V processors. Register settings configure the interface bus width, format

(8/10/12/16/20/24-bit), and rising or falling edge latching. The appropriate registers must be configured to describe

which format of video is being sent to the SiI9134 transmitter. This information travels over the HDMI link in CEA-

861D Active Video Information (AVI) packets. The transmitter also supports dual-edge clocking using 12 data pins.

Configuration to Support Deep-color

The SiI9134 transmitter provides support for Deep Color video data up to the maximum specified link speed of

2.25 Gbps (225 MHz internal clock rate for the Deep Color packetized data). It supports both 30-bit (10-bits per pixel

component) and 36-bit (12-bits per pixel component) video input formats, and converts the data to 8-bit packets for

encryption and TMDS encoding for transferring across the TMDS link.

When the input data width is wider than desired, the device can be programmed to dither or truncate the video data to

the desired size. For instance, if the input data width is 12 bits per pixel component, but the sink device only supports 10

bits, the transmitter can be programmed either to dither or to truncate the 12-bit input data to the desired 10-bit output

data. Dither processing is the final block in the video processing path and occurs after all other video processing has

been performed.

Silicon Image

Confidential

for

Co-Edifice Video

Technology

Internal Use Only

SiI9134 HDMI Deep Color Transmitter

Data Sheet

Silicon Image, Inc.

CONFIDENTIAL

Common Video Input Formats

Table 2 lists the video input formats that the SiI9134 transmitter supports.

Table 2. Video Input Formats Example

Color

Space

Video

Format

Input

Channels

Bus

Width

1, 2

HSYNC/

VSYNC

Input Pixel Clock (MHz)

480i

VGA/4

80p

XGA 720p 1080i SXGA 1080p UXGA Notes

RGB 4:4:4 3 36 Separate 27 25/27 — 74.25 74.25 108 148.5 — —

3 30 Separate 27 25/27 — 74.25 74.25 108 148.5 — —

3 24 Separate 27 25/27 65 74.25 74.25 108 148.5 162 —

1.5 12 Separate 27 25/27 65 74.25 74.25 — — — 3

1.5 15 Separate 27 25/27 65 74.25 74.25 — — — 3

1.5 18 Separate 27 25/27 65 74.25 74.25 — — — 3

YCbCr 4:4:4 3 36 Separate 27 27 — 74.25 74.25 — 148.5 — —

3 30 Separate 27 27 — 74.25 74.25 — 148.5 — —

3 24 Separate 27 27 — 74.25 74.25 — 148.5 — —

1.5 12 Separate 27 27 — 74.25 74.25 — — — 3

1.5 15 Separate 27 25/27 65 74.25 74.25 — — — 3

1.5 18 Separate 27 25/27 65 74.25 74.25 — — — 3

4:2:2

16/20/24 Separate 27 27 — 74.25 74.25 — 148.5 — —

Embedded 27 27 — 74.25 74.25 — 148.5 — 4

1 8/10/12

Separate 27 54 — 148.5 148.5 — — — —

Embedded 27 54 — 148.5 148.5 — — — 4

BTA-

T1004

— 54 — — — — — — 4 , 6

Notes:

1. Bus widths of 8, 10, or 12 bits use one channel. Bus widths of 16, 20, or 24 bits with 4:2:2 data sequences use two

data channels.

2. Latching edge is programmable.

3. These formats use dual-edge clocking.

4. If embedded syncs are provided, then DE is generated internally from SAV/EAV sequences. Embedded syncs use

656 SAV/EAV sequences of FF, 00, 00, XY.

5. 480i must be input at 27 MHz using pixel replication to be transmitted across the HDMI link.

6. BTA-T1004 format is defined for a single-channel (8/10/12-bit) bus with encoded syncs.

Embedded Sync Decoding

The SiI9134 transmitter can create DE, HSYNC, and VSYNC signals from the Start of Active Video (SAV) and End of

Active Video (EAV) codes within the 656 video stream. HDCP is not supported in this mode.

Data Enable Generator

The transmitter includes logic to construct a DE signal from the incoming HSYNC, VSYNC, and clock. Registers are

programmed to enable the DE signal to define the size of the active display region. This feature is useful when

interfacing to MPEG decoders that do not provide a specific DE output signal.

Re-sampling

Re-sampling (up-sampling/decimation) blocks allow conversion of 4:4:4 data to 4:2:2 and of 4:2:2 data to 4:4:4 for

transmission over the HDMI link.

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