Intel I210 Ethernet Controller: Low Power, GbE Solution with Advanced Features

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"Intel® Ethernet Controller I210是一款单端口、紧凑型、低功耗组件，支持千兆位以太网（GbE）设计。它集成了GbE媒体访问控制（MAC）、物理层（PHY）端口和一个可连接到外部PHY的SGMII/SerDes端口。I210支持PCI Express（PCIe）v2.1（2.5GT/s）x1接口，并带有切换电压调节器（iSVR）。" Intel I210以太网控制器具有以下关键特性： 1. **小尺寸封装**：采用9x9mm的小型封装，适合空间有限的设计应用。 2. **PCI Express v2.1**：支持2.5吉比特每秒的数据传输速率，提供单通道连接，结合了iSVR，可优化电源管理。 3. **集成非易失性内存（iNVM）**：提供了一种存储配置和固件的内置方法，无需外部存储器。 4. **三种单端口型号**：包括SerDes、Copper和Copper IT，分别适用于不同类型的网络连接需求。 5. **性价比高的Intel® Ethernet Controller I211**：为更经济高效的解决方案提供了选择。 6. **平台能效**：符合IEEE 802.3az Energy Efficient Ethernet（EEE）标准，降低能耗。同时，支持ECMA-393和Windows*的节能代理卸载。 7. **高级功能**： - 支持商业和工业温度范围：0到70°C或-40到85°C。 - 集成音频视频桥接（AVB），用于多媒体传输。 - IEEE 1588/802.1AS精确时间同步，确保网络中的时间一致性。 - IEEE 802.1Qav流量整形，软件扩展增强带宽管理。 - 支持大帧（Jumbo frames）传输。 - 中断调制、VLAN支持、IP校验和卸载，优化系统性能。 - PCIe OBFF功能，提升系统电源管理效率。 - 四个发送队列和四个接收队列，支持多任务处理。 - RSS（接收侧扩展）和MSI-X（多源中断扩展），降低多核系统的CPU利用率。 - 先进的电缆诊断、自动MDI-X功能，简化网络故障排查。 - ECC内存，用于数据包缓冲区，提高数据完整性。 - 四个软件可定义引脚（SDPs），实现灵活的硬件扩展。 8. **管理能力**：支持NC-SI（网络控制简单接口），提供远程管理功能。这些特性使得Intel I210成为各种应用场景的理想选择，包括数据中心、企业网络、嵌入式系统和工业自动化，因为它能够提供高性能、低功耗和强大的管理功能。同时，其广泛的兼容性和高级特性确保了在网络环境中稳定、高效的工作。

Ethernet Controller I210 —Introduction

1.6 I210 and I211 Options

Table 1-10 lists the main differences between features supported by the I210 and I211.

1.7 Overview of Changes Compared to the I350

The following section describes the modifications designed in the I210 compared to the I350.

1.7.1 Network Interface

1.7.1.1 Energy Efficient Ethernet (IEEE802.3AZ)

The I210 supports negotiation and link transition to a Low Power Idle (LPI) state as defined in the

IEEE802.3az (EEE) standard. Energy Efficient Ethernet (EEE) is supported only in the internal copper

PHY mode and for the following technologies:

• 1000BASE-T

• 100BASE-TX

EEE enables reduction of the I210 power consumption as a function of link utilization. In addition, the

I210 enables overall system power reduction as a function of link utilization by reporting increased

latency tolerance values via PCIe LTR messages when link is in the LPI state. For more information,

refer to Section 3.7.7.

LAN disable functionality (equivalent to Static device off

functionality in the I210/I211)

PCIe function disable Y Y Y Y

Dynamic device off Y

EEE YYYN

DMA coalescing Y N Y N

OBFF/PE_WAKE_N Y

NNN

1. Feature not functional if enabled together with dynamic device off.

2. Feature not functional if enabled together with static device off (such as LAN disable).

3. Disabled by default in Flash due to the lack of OBFF enabled platforms at initial release.

Table 1-10. I210 9x9 QFN and I211 9x9 QFN Package Feature

Feature I210 I211

SerDes/SGMII port Yes (for SerDes I210 SKU only) Not supported.

Manageability Yes Not supported

Integrated SVR and LVR control Supported Supported

82574 pinout compatibility Footprint compatibility only Not supported

82583V pinout compatibility Not supported Footprint compatibility only

Table 1-9. Power Management Features

Feature I210 I211 I350 82574

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Introduction—Ethernet Controller I210

1.7.1.2 OBFF

The I210 support Optimized Buffer Flush Fill (OBFF) for synchronizing platform I/Os and optimizing CPU

sleep states. The support is via the PE_WAKE_N pin only.

1.7.2 Audio and Video Bridging Support

See Section 1.3.1 for details on IEEE 802.1Qav support.

1.7.2.1 Tx Timestamp

The I210 supports three types of transmit timestamps:

1. Reporting back of the timestamp in the transmit descriptor.

2. Inserting the timestamp in the packet sent.

3. Recording the timestamp of selected packet in a register (legacy behavior).

Transmit timestamp is described in Section 7.0, Inline Functions.

1.7.3 Virtualization

SR-IOV and VMDq is not supported in hardware by the I210. The I210 can still be used in virtualized

systems where the VM switching is done in software.

1.7.3.1 Number of Exact Match Filters

The number of RAH/RAL registers is 16.

1.7.4 Host Interface

1.7.4.1 MSI-X Support

The number of MSI-X vectors supported by the I210 changed to 5. For further information, refer to

Section 7.3.

1.7.4.2 Optimized Buffer Flush/FILL (OBFF)

The I210 supports the PCIe OBFF specification, using the PE_WAKE_N signal to enable synchronizing

device activity and optimize power management of memory, CPU and RC internal circuitry. By

synchronizing PCIe activity of PCIe endpoints, the system can stay in lower power states for a longer

duration.

When in buffer fill (DMA coalescing) operating mode, the PCIe link is optionally placed in a L1 power

saving state and DMA activity is placed on hold. The I210 moves into buffer flush mode when internal

receive buffers pass a pre-determined threshold value, a watchdog timer expires, or the PCIe interface

invokes a move out of buffer fill state. Further information can be found in Section 5.9.

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Ethernet Controller I210 —Introduction

1.7.5 Manageability

1.7.5.1 DMTF MCTP Protocol Over PCIe

The I210 enables reporting and controlling all information exposed in a LOM device via NC-SI using the

MCTP protocol over PCIe in addition to SMBus. The MCTP interface over PCIe is used by the MC to

control the NIC and for pass through traffic. For more information, refer to Section 10.7.

1.7.5.2 Flash Structures

Management related Flash structures were updated. For further information see Chapter 6.0.

1.7.5.3 Improved Support of Shared MAC and Shared IP

The I210 supports better filtering in systems when the MAC or the IP is shared with the host. This

support is achieved using additional filtering capabilities as described in Section 10.3.1 and can be

controlled using a new set of NC-SI OEM commands as the functionality described in Section 10.6.3.14

and Section 10.3.7.

1.7.5.4 Simplified SMBus TCO Status and Filter Setting

The TCO status in SMBus received packet was reduced to eight bytes and most of the information was

removed in order to keep only the information relevant to the MCs. See Section 10.5.9.2.1.1 for

details.

In addition, a generic command is used to set the most common filtering options independently of the

actual filters implementation. See Section 10.5.9.1.7 for details.

1.7.5.5 Diagnostic Commands

Commands were added to the NC-SI and legacy SMBus to query the identity of the I210 and the

firmware versions currently running on the I210. See Section 10.5.9.2.7 and Section 10.6.3.16.1 for

details.

1.7.6 BOM Cost Reduction

1.7.6.1 On-chip 0.9V SVR Control

The I210 includes a fully integrated on-chip Switching Voltage Regulator (SVR) that can be used to

generate a 0.9V power supply without the need for a higher cost on-board 0.9V voltage regulator (refer

to Section 3.6).

1.8 Device Data Flows

1.8.1 Transmit Data Flow

Table 1-11 lists a high level description of all data/control transformation steps needed for sending

Ethernet packets to the line.

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Introduction—Ethernet Controller I210

1.8.2 Receive Data Flow

Table 1-12 lists a high level description of all data/control transformation steps needed for receiving

Ethernet packets.

Table 1-11. Transmit Data Flow

Step Description

The host creates a descriptor ring and configures one of the I210's transmit queues with the address location,

length, head and tail pointers of the ring (one of 4 available Tx queues).

The host is requested by the TCP/IP stack to transmit a packet, it gets the packet data within one or more data

buffers.

The host initializes descriptor(s) that point to the data buffer(s) and have additional control parameters that

describe the needed hardware functionality. The host places that descriptor in the correct location at the

appropriate Tx ring.

4 The host updates the appropriate queue tail pointer (TDT)

The I210's DMA senses a change of a specific TDT and as a result sends a PCIe request to fetch the descriptor(s)

from host memory.

The descriptor(s) content is received in a PCIe read completion and is written to the appropriate location in the

descriptor queue internal cache.

The DMA fetches the next descriptor from the internal cache and processes its content. As a result, the DMA sends

PCIe requests to fetch the packet data from system memory.

The packet data is received from PCIe completions and passes through the transmit DMA that performs all

programmed data manipulations (various CPU off loading tasks as checksum off load, TSO off load, etc.) on the

packet data on the fly.

While the packet is passing through the DMA, it is stored into the transmit FIFO. After the entire packet is stored in

the transmit FIFO, it is forwarded to the transmit switch module.

The transmit switch arbitrates between host and management packets and eventually forwards the packet to the

MAC.

11 The MAC appends the L2 CRC to the packet and sends the packet to the line using a pre-configured interface.

12 When all the PCIe completions for a given packet are done, the DMA updates the appropriate descriptor(s).

After enough descriptors are gathered for write back or the interrupt moderation timer expires, the descriptors are

written back to host memory using PCIe posted writes. Alternatively, the head pointer can only be written back.

After the interrupt moderation timer expires, an interrupt is generated to notify the host device driver that the

specific packet has been read to the I210 and the driver can release the buffers.

Table 1-12. Receive Data Flow

Step Description

The host creates a descriptor ring and configures one of the I210's receive queues with the address location,

length, head, and tail pointers of the ring (one of 4 available Rx queues).

The host initializes descriptors that point to empty data buffers. The host places these descriptors in the correct

location at the appropriate Rx ring.

3 The host updates the appropriate queue tail pointer (RDT).

The I210's DMA senses a change of a specific RDT and as a result sends a PCIe request to fetch the descriptors

from host memory.

The descriptors content is received in a PCIe read completion and is written to the appropriate location in the

descriptor queue internal cache.

6 A packet enters the Rx MAC. The Rx MAC checks the CRC of the packet.

7 The MAC forwards the packet to an Rx filter.

If the packet matches the pre-programmed criteria of the Rx filtering, it is forwarded to the Rx FIFO. VLAN and

CRC are optionally stripped from the packet and L3/L4 checksum are checked and the destination queue is fixed.

The receive DMA fetches the next descriptor from the internal cache of the appropriate queue to be used for the

next received packet.

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Ethernet Controller I210 —Introduction

After the entire packet is placed into the Rx FIFO, the receive DMA posts the packet data to the location indicated

by the descriptor through the PCIe interface. If the packet size is greater than the buffer size, more descriptors are

fetched and their buffers are used for the received packet.

When the packet is placed into host memory, the receive DMA updates all the descriptor(s) that were used by

packet data.

After enough descriptors are gathered for write back or the interrupt moderation timer expires or the packet

requires immediate forwarding, the receive DMA writes back the descriptor content along with status bits that

indicate the packet information including what off loads were done on that packet.

After the interrupt moderation timer completes or an immediate packet is received, the I210 initiates an interrupt

to the host to indicate that a new received packet is already in host memory.

Host reads the packet data and sends it to the TCP/IP stack for further processing. The host releases the

associated buffers and descriptors once they are no longer in use.

Table 1-12. Receive Data Flow (Continued)

Step Description

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