低温CMOS红外焦平面阵列新型读出结构

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本文主要探讨了一种新型的低温CMOS读取技术，旨在提高红外焦平面阵列（Infrared Focal Plane Array, IR FPA）的性能。这种创新的结构被称为开关电流集成（Switch Current Integration, SCI）架构，它在《固态电路》（IEEE Journal of Solid-State Circuits）期刊的第32卷第8期中发表。论文重点介绍了以下关键内容： 1. **创新设计**： SCI结构利用了共享缓冲直接注入（Share-Buffered Direct Injection, SBDI）偏置技术和阵列外集成电容器（Off-Focal Plane Array, off-FPA）结构，实现了对IR FPA的高效读出接口电路。这种设计允许实现尺寸为50x50微米²的像素，显著提高了读取效率。 2. **性能提升**：通过结合相关双采样（Correlated Double Sampling, CDS）阶段和动态放电输出（Dynamic Discharging Output, DDO）环节，该读出结构在保持低功耗的同时，显著改善了噪声控制和速度性能。这使得在低温环境下（如77K），芯片能有效执行读出任务并展现优化后的特性。 3. **技术实现**：一篇实验性的SCI读取芯片在0.8微米双poly双金属（Double-Poly Double-Metal, DPDM）n-well CMOS工艺中被设计和制造。实验结果显示，使用4V和8V电源电压时，芯片在77K时的读取功能得到了验证，并且证明了其性能改进。 4. **实际应用**：本文提供的技术不仅展示了理论上的优势，而且具有实际的应用价值。通过这种低温CMOS读出方法，红外成像系统可以更好地适应严苛的工作环境，例如太空探测、遥感和低温科学实验。这项研究对于推动红外焦平面阵列在低温环境下的高性能应用具有重要意义，特别是在需要高灵敏度和快速响应的应用领域。通过采用SCI架构，CMOS技术在极端条件下也能展现出其出色的潜力。

1192 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 8, AUGUST 1997

A New Cryogenic CMOS Readout

Structure for Infrared Focal Plane Array

Chih-Cheng Hsieh, Chung-Yu Wu, Senior Member, IEEE, and Tai-Ping Sun

Abstract— A new current readout structure for the infrared

(IR) focal-plane-array (FPA), called the switch-current integra-

tion (SCI) structure, is presented in this paper. By applying

the share-buffered direct-injection (SBDI) biasing technique and

off focal-plane-array (off-FPA) integration capacitor structure,

a high-performance readout interface circuit for the IR FPA is

realized with a pixel size of 50



. Moreover, the correlated

double sampling (CDS) stage and dynamic discharging output

stage are utilized to improve noise and speed performance of the

readout structure under low power dissipation. An experimental

SCI readout chip has been designed and fabricated in 0.8-



double-poly-double-metal (DPDM) n-well CMOS technology. The

measurement results of the fabricated readout chip at 77 K

with 4 and 8 V supply voltages have successfully veriﬁed both

the readout function and the performance improvement. The

fabricated chip has a maximum charge capacity of 1.12

electrons, a maximum transimpedance of 1



, and ae

active power dissipation of 30 mW. The proposed CMOS SCI

structure can be applied to various cryogenic IR FPA’s.

Index Terms—CMOS integrated circuit, cryogenic electronics,

focal plane array, readout circuit.

I. INTRODUCTION

N the design of the infrared (IR) focal-plane array (FPA),

high resolution has become a common requirement in many

applications. This leads to large array format and small pixel

size. Due to the small pixel size, it is difﬁcult in the design

of high-resolution large IR FPA’s to implement complex

high-performance readout input circuits (e.g., buffered direct

injection (BDI) [1], [2], capacitive transimpedance ampliﬁer

(CTIA) [3], [4], and chopper-stabilized input circuit (CSI) [5])

with a large enough in-pixel integration capacitor. Usually one

uses a simple readout circuit to maintain a large enough in-

pixel capacitor. Thus, the readout performance (e.g., dynamic

range and signal-to-noise ratio) is degraded. Moreover, the

strict constraint on the unit-cell power dissipation also in-

creases the difﬁculty to obtain the good readout performance

in a large format IR FPA.

So far, several developed simple current readout schemes

such as the direct injection (DI) [1], [6], [7], the source

follower per detector (SFD) [8], [9], and the gate-modulation

input (GMI) [8], [10], have been developed and have become

commonly used structures in the IR FPA readout chip. In these

Manuscript received August 30, 1996; revised March 6, 1997.

C.-C. Hsieh and C.-Y. Wu are with the Integrated Circuits and Systems

Laboratory, Department of Electronics Engineering and Institute of Electron-

ics, National Chiao Tung University, Hsinchu, Taiwan 300, R.O.C.

T.-P. Sun is with the Chung Shang Institute of Science and Technology,

Lung-Tan, Taiwan, R.O.C.

Publisher Item Identiﬁer S 0018-9200(97)05315-8.

readout schemes, a simple circuit is used to satisfy both pixel

size and power dissipation limitations while sacriﬁcing some

readout performance such as the poor injection efﬁciency,

the detector bias nonuniformity, and the noise ﬁgures. In the

applications of long wavelength infrared (LWIR) detection,

a large integration capacitor is needed because of the large

amount of both background photons and dark currents in the

photodiode. Thus, a large common off-focal-plane integration

capacitor is used in the readout circuit to meet the requirement

while minimizing the chip area [11], [12]. In performing the

signal integration, the conventional multiplexed electronically

scanned array (MESA) [11] is used to select the detector

directly through MOS switches and the direct injection gate

(DIG). In the operation, the inevitable switching noise is easily

coupled to the detector bias. Moreover, using the DIG as a

buffer, it has the constraints on detector bias stability and the

same poor readout performance as in the DI readout circuit.

In this paper, a new current readout structure for the IR

FPA, called the switch-current integration (SCI) structure,

is proposed to solve the above mentioned problems and

improve the readout performance. It has been shown from

both simulation and experimental results that the proposed SCI

readout structure can achieve good readout performance in a

small pixel size through the use of the SCI technique, the off-

FPA shared integration capacitors, and the previously proposed

share-buffered direct injection (SBDI) input circuit [13], [14].

The circuit structure, readout strategy, and circuit performance

of the new SCI readout structure are described in Section II.

In Section III, both simulation results and experimental results

of the fabricated SCI readout chip are presented. Finally, a

conclusion is given.

II. S

WITCH-CURRENT INTEGRATION

(SCI) READOUT STRUCTURE

Fig. 1 shows the block diagram of the proposed SCI readout

structure which is composed of three major parts: the unit-cell

input stage, the shared off-FPA integration capacitor stage, and

the common output stage. The circuit operation is explained

as follows. The photon-generated current in the detector cell is

buffered and switched one row at one time by the vertical row

shift register to the shared off-FPA integration capacitor and

integrated. After an integrating interval, the voltage signal is

sampled, one column after the other by the horizontal column

shift register to the common output stage serially. In the

following, the detailed circuit structure and the operational

principle of each block are described.

0018–9200/97$10.00  1997 IEEE

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