ARM7DI技术规格说明书：ARM处理器的详细介绍

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ARM7DI数据表是一份详尽的技术文档，由Advanced RISC Machines (ARM)有限公司于1994年12月发布，版权所有。这份数据表专门介绍了ARM7DI处理器，它是ARM系列中的一个成员，其目标是为嵌入式系统和微控制器提供高性能、低功耗的解决方案。 ARM7DI是一款精简指令集计算机(RISC)架构，它具有高效的指令执行能力，适合对内存带宽需求不高的应用。它包括了诸如处理核心、缓存、以及与外部接口兼容的特性，旨在简化设计过程并提高系统的实时性能。文档编号ARMDDI0027D，表明这是ARM官方发布的第27版技术资料。数据表中的"AdvancedRISCMachines"部分强调了ARM在RISC技术领域的领导地位，以及BlackICE和ICEbreaker等商标的含义，这些都反映了ARM对于创新和高质量产品的承诺。该数据表仅允许在事先获得版权持有人书面许可的情况下复制或改编。值得注意的是，文档中包含了关于持续改进和可能存在的变动的记录，例如列出的“Change Log”部分，列出了自A版本以来的更新日期、修改人以及具体更改内容。这表明ARM7DI在不断发展，用户应持续关注最新的修订版以获取最准确的产品信息。此外，数据表还强调了使用该产品的注意事项。ARM公司并不对因使用文档中的信息、信息中的错误或遗漏，或者产品错误使用导致的任何损失或损害承担责任。这表明用户在使用ARM7DI时应自行负责，并且需遵循制造商的指南以确保最佳性能和安全性。 ARM7DI数据表是一份重要的参考资料，为开发者提供了关于ARM7DI处理器的关键特性和使用细节，但同时也明确指出了责任边界和适用范围。对于那些寻求在嵌入式系统和微控制器设计中采用ARM技术的工程师来说，理解和遵循这份数据表至关重要。

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ARM7DI Data Sheet

3.1.2 Conﬁguration Bits for Backward Compatibility

The other two inputs, PROG32 and DATA32 are used for backward compatibility with earlier ARM

processors (see 12.0: Appendix - Backward Compatibility) but should normally be set to 1. This configuration

extends the address space to 32 bits, introduces major changes in the programmer's model as described

below, and provides support for running existing 26 bit programs in the 32 bit environment. This mode is

recommended for compatibility with future ARM processors and all new code should be written to use

only the 32 bit operating modes.

Because the original ARM instruction set has been modified to accommodate 32 bit operation there are

certain additional restrictions which programmers must be aware of. These are indicated in the text by the

words shall and shall not. Reference should also be made to the ARM Application Notes “Rules for ARM Code

Writers” and “Notes for ARM Code Writers”, available from your supplier.

3.2 Operating Mode Selection

ARM7DI has a 32 bit data bus and a 32 bit address bus. The processor supports byte (8 bit) and word (32 bit)

data types, where words must be aligned to four byte boundaries. Instructions are exactly one word long,

and data operations (eg ADD) are only performed on word quantities. Load and store operations can

transfer either bytes or words.

Big Endian

Higher Address 31 24 23 16 15 8 7 0 Word Address

8910118

45674

01230

Lower Address

• Most signiﬁcant byte is at lowest address

• Word is addressed by byte address of most signiﬁcant byte

Figure 5: Big Endian addresses of bytes within words

Programmer's Model

ARM7DI supports six modes of operation:

(1) User mode (usr): the normal program execution state

(2) FIQ mode (fiq): designed to support a data transfer or channel process

(3) IRQ mode (irq): used for general purpose interrupt handling

(4) Supervisor mode (svc): a protected mode for the operating system

(5) Abort mode (abt): entered after a data or instruction prefetch abort

(6) Undefined mode (und): entered when an undefined instruction is executed

Mode changes may be made under software control or may be brought about by external interrupts or

exception processing. Most application programs will execute in User mode. The other modes, known as

privileged modes, will be entered to service interrupts or exceptions or to access protected resources.

3.3 Registers

The processor has a total of 37 registers made up of 31 general 32 bit registers and 6 status registers. At any

one time 16 general registers (R0 to R15) and one or two status registers are visible to the programmer. The

visible registers depend on the processor mode. The other registers, known as the banked registers, are

switched in to support IRQ, FIQ, Supervisor, Abort and Undefined mode processing. Figure 6: Register

Organisation shows how the registers are arranged, with the banked registers shaded.

In all modes 16 registers, R0 to R15, are directly accessible. All registers except R15 are general purpose and

may be used to hold data or address values. Register R15 holds the Program Counter (PC). When R15 is

read, bits [1:0] are zero and bits [31:2] contain the PC. A seventeenth register (the CPSR - Current Program

Status Register) is also accessible. It contains condition code flags and the current mode bits and may be

thought of as an extension to the PC.

R14 is used as the subroutine link register and receives a copy of R15 when a Branch and Link instruction

is executed. It may be treated as a general purpose register at all other times. R14_svc, R14_irq, R14_fiq,

R14_abt and R14_und are used similarly to hold the return values of R15 when interrupts and exceptions

arise, or when Branch and Link instructions are executed within interrupt or exception routines.

Programmer's Model

Figure 7: Format of the Program Status Registers (PSRs)

The format of the Program Status Registers is shown in Figure 7: Format of the Program Status Registers

(PSRs). The N, Z, C and V bits are the condition code flags. The condition code flags in the CPSR may be

changed as a result of arithmetic and logical operations in the processor and may be tested by all

instructions to determine if the instruction is to be executed.

The I and F bits are the interrupt disable bits. The I bit disables IRQ interrupts when it is set and the F bit

disables FIQ interrupts when it is set. The M0, M1, M2, M3 and M4 bits (M[4:0]) are the mode bits, and these

determine the mode in which the processor operates. The interpretation of the mode bits is shown in Table

2: The Mode Bits. Not all bit combinations define a valid processor mode. Only those explicitly described

shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0],

the processor will enter an unrecoverable state. If this occurs, reset should be applied.

The bottom 28 bits of a PSR (incorporating I, F and M[4:0]) are known collectively as the control bits. These

will change when an exception arises and in addition can be manipulated by software when the processor

is in a privileged mode. Unused bits in the PSRs are reserved and their state shall be preserved when

changing the flag or control bits. Programs shall not rely on specific values from the reserved bits when

checking the PSR status, since they may read as one or zero in future processors.

M[4:0] Mode Accessible register set

10000 User PC, R14..R0 CPSR

10001 FIQ PC, R14_fiq..R8_fiq, R7..R0 CPSR, SPSR_fiq

10010 IRQ PC, R14_irq..R13_irq, R12..R0 CPSR, SPSR_irq

10011 Supervisor PC, R14_svc..R13_svc, R12..R0 CPSR, SPSR_svc

10111 Abort PC, R14_abt..R13_abt, R12..R0 CPSR, SPSR_abt

11011 Undeﬁned PC, R14_und..R13_und, R12..R0 CPSR, SPSR_und

Table 2: The Mode Bits

0123456782728293031

M0M1M2M3M4.FIVCZN

Overflow

Carry / Borrow / Extend

Zero

Negative / Less Than

Mode bits

FIQ disable

IRQ disable

...

flags

control

ARM7DI Data Sheet

3.4 Exceptions

Exceptions arise whenever there is a need for the normal flow of program execution to be broken, so that

(for example) the processor can be diverted to handle an interrupt from a peripheral. The processor state

just prior to handling the exception must be preserved so that the original program can be resumed when

the exception routine has completed. Many exceptions may arise at the same time.

ARM7DI handles exceptions by making use of the banked registers to save state. The old PC and CPSR

contents are copied into the appropriate R14 and SPSR and the PC and mode bits in the CPSR bits are forced

to a value which depends on the exception. Interrupt disable flags are set where required to prevent

otherwise unmanageable nestings of exceptions. In the case of a re-entrant interrupt handler, R14 and the

SPSR should be saved onto a stack in main memory before re-enabling the interrupt; when transferring the

SPSR register to and from a stack, it is important to transfer the whole 32 bit value, and not just the flag or

control fields. When multiple exceptions arise simultaneously, a fixed priority determines the order in

which they are handled. This is listed later in Section 3.4.7: Exception Priorities on page 23.

3.4.1 FIQ

The FIQ (Fast Interrupt reQuest) exception is externally generated by taking the nFIQ input LOW. This

input can except either synchronous or asynchronous transitions, depending on the state of the ISYNC

input signal. When ISYNC is LOW, nFIQ (and nIRQ) are considered asynchronous, and a cycle delay for

synchronisation is incurred before the interrupt can affect the processor flow. FIQ is designed to support a

data transfer or channel process, and has sufficient private registers to remove the need for register saving

in such applications (thus minimising the overhead of context switching). The FIQ exception may be

disabled by setting the F flag in the CPSR (but note that this is not possible from User mode). If the F flag is

clear, ARM7DI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction.

When a FIQ is detected, ARM7DI:

(1) Saves the address of the next instruction to be executed plus 4 in R14_fiq; saves CPSR in SPSR_fiq

(2) Forces M[4:0]=10001 (FIQ mode) and sets the F and I bits in the CPSR

(3) Forces the PC to fetch the next instruction from address 0x1C

To return normally from FIQ, use SUBS PC, R14_fiq,#4 which will restore both the PC (from R14) and the

CPSR (from SPSR_fiq) and resume execution of the interrupted code.

3.4.2 IRQ

The IRQ (Interrupt ReQuest) exception is a normal interrupt caused by a LOW level on the nIRQ input. It

has a lower priority than FIQ, and is masked out when a FIQ sequence is entered. Its effect may be masked

out at any time by setting the I bit in the CPSR (but note that this is not possible from User mode). If the I

flag is clear, ARM7DI checks for a LOW level on the output of the IRQ synchroniser at the end of each

instruction. Note that nIRQ may also have synchronous or asynchronous timing, depending on the state of

the ISYNC input. When an IRQ is detected, ARM7DI:

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