QuartusII10.1SignalTap使用指南：快速掌握逻辑分析器

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"SignalTap使用手册，Quartus II Handbook Version 10.1 Volume 3: Verification，Altera公司2010年12月发布" SignalTap是一款由Altera公司开发的嵌入式逻辑分析工具，它主要用于FPGA（Field Programmable Gate Array）设计的调试和验证。在Quartus II集成开发环境中，SignalTap为用户提供了实时、低开销的调试功能，使开发者能够更快速地理解和解决设计中的问题。在Quartus II Handbook Version 10.1 Volume 3中，"Design Debugging Using the SignalTap II Logic Analyzer"这一章节详细介绍了如何利用SignalTap II进行设计调试。该手册的内容可能涵盖以下几个关键知识点： 1. **SignalTap II安装与配置**：首先，用户需要了解如何在Quartus II环境下安装和配置SignalTap II，包括创建新的SignalTap工程、设置所需的输入信号以及配置触发条件。 2. **逻辑分析器的基本概念**：理解逻辑分析器的工作原理，如何捕获和存储设计中的信号值，以及如何通过图形界面查看这些数据。 3. **选择监控信号**：在调试过程中，正确选择需要监控的信号至关重要。SignalTap II允许用户从设计中选择感兴趣的信号，以便在运行时观察其变化。 4. **触发系统设置**：学习如何定义触发条件，确保在特定事件发生时开始捕获数据。这有助于定位问题，因为它允许用户在问题出现时查看设计的状态。 5. **实时查看和分析**：SignalTap II提供了一个实时查看器，让用户能够在FPGA运行时查看信号波形，从而对设计的行为有直观的理解。 6. **优化调试性能**：由于SignalTap II是嵌入式的，因此需要考虑其对设计资源的影响。手册可能会介绍如何优化设置以减少对系统性能的影响，同时保持足够的调试功能。 7. **与仿真结果对比**：SignalTap II的数据可以与软件仿真结果进行比较，帮助验证硬件实现是否符合预期。 8. **故障排查和问题解决**：手册可能会提供一些常见的调试问题及其解决方案，帮助用户快速解决遇到的问题。 9. **版本更新和兼容性**：由于手册是2010年12月发布的，因此可能涉及到当时版本的特性和限制，用户应关注设备规格的最新版本以获取最新信息。 SignalTap II是Altera FPGA设计者的重要工具，它简化了复杂设计的调试过程，使得硬件工程师能够高效地验证和优化他们的设计。通过详细阅读和实践手册中的内容，用户将能够熟练掌握SignalTap II的使用，提高开发效率。

15–12 Chapter 15: Design Debugging Using the SignalTap II Logic Analyzer

Configure the SignalTap II Logic Analyzer

Quartus II Handbook Version 10.1 Volume 3: Verification December 2010 Altera Corporation

Untappable Signals

Not all of the post-fitting signals in your design are available in the SignalTap II :

post-fitting filter in the Node Finder dialog box. The following signal types cannot be

tapped:

■ Post-fit output pins—You cannot tap a post-fit output pin directly. To make an

output signal visible, tap the register or buffer that drives the output pin. This

includes pins defined as bidirectional.

■ Signals that are part of a carry chain—You cannot tap the carry out (

cout0

cout1

) signal of a logic element. Due to architectural restrictions, the carry out

signal can only feed the carry in of another LE.

■ JTAG Signals—You cannot tap the JTAG control (

TCK

TDI

TDO

, and

TMS

) signals.

■ ALTGXB megafunction—You cannot directly tap any ports of an ALTGXB

instantiation.

■ LV DS —You cannot tap the data output from a serializer/deserializer (SERDES)

block.

■ DQ, DQS Signals—You cannot directly tap the

DQS

signals in a DDR/DDRII

design.

Adding Signals with a Plug-In

Instead of adding individual or grouped signals through the Node Finder, you can

add groups of relevant signals of a particular type of IP with a plug-in. The

SignalTap II Logic Analyzer comes with one plug-in already installed for the Nios II

processor. Besides easy signal addition, plug-ins also provide features such as

pre-designed mnemonic tables, useful for trigger creation and data viewing, as well as

the ability to disassemble code in captured data.

The Nios II plug-in, for example, creates one mnemonic table in the Setup tab and two

tables in the Data tab:

■ Nios II Instruction (Setup tab)—Capture all the required signals for triggering on

a selected instruction address.

■ Nios II Instance Address (Data tab)—Display address of executed instructions in

hexadecimal format or as a programming symbol name if defined in an optional

Executable and Linking Format (.elf) file.

■ Nios II Disassembly (Data tab)—Displays disassembled code from the

corresponding address.

For information about the other features plug-ins provided, refer to “Define Triggers”

on page 15–25 and “View, Analyze, and Use Captured Data” on page 15–55.

To add signals to the .stp using a plug-in, perform the following steps after running

Analysis and Elaboration on your design:

1. Right-click in the node list. On the Add Nodes with Plug-In submenu, choose the

plug-in you want to use, such as the included plug-in named Nios II.

1 If the IP for the selected plug-in does not exist in your design, a message

informs you that you cannot use the selected plug-in.

Chapter 15: Design Debugging Using the SignalTap II Logic Analyzer 15–13

Configure the SignalTap II Logic Analyzer

December 2010 Altera Corporation Quartus II Handbook Version 10.1 Volume 3: Verification

2. The Select Hierarchy Level dialog box appears showing the IP hierarchy of your

design. Select the IP that contains the signals you want to monitor with the plug-in

and click OK.

3. If all the signals in the plug-in are available, a dialog box might appear, depending

on the plug-in selected, where you can specify options for the plug-in. With the

Nios II plug-in, you can optionally select an .elf containing program symbols from

your Nios II Integrated Development Environment (IDE) software design. Specify

options for the selected plug-in as desired and click OK.

1 To make sure all the required signals are available, in the Quartus II Analysis &

Synthesis settings, turn on Create debugging nodes for IP cores.

All the signals included in the plug-in are added to the node list.

Adding Finite State Machine State Encoding Registers

Finding the signals to debug Finite State Machines (FSM) can be challenging. Finding

nodes from the post-fit netlist may be impossible, as FSM encoding signals may be

changed or optimized away during synthesis and place-and-route. If you can find all

of the relevant nodes in the post-fit netlist or you used the nodes from the

pre-synthesis netlist, an additional step is required to find and map FSM signal values

to the state names that you specified in your HDL.

The SignalTap II Logic Analyzer GUI can detect FSMs in your compiled design. The

SignalTap II Logic Analyzer configuration automatically tracks the FSM state signals

as well as state encoding through the compilation process. Shortcut menu commands

from the SignalTap II Logic Analyzer GUI allow you to add all of the FSM state

signals to your logic analyzer with a single command. For each FSM added to your

SignalTap II configuration, the FSM debugging feature adds a mnemonic table to map

the signal values to the state enumeration that you provided in your source code. The

mnemonic tables enable you to visualize state machine transitions in the waveform

viewer. The FSM debugging feature supports adding FSM signals from both the

pre-synthesis and post-fit netlists.

Figure 15–4 shows the waveform viewer with decoded signal values from a state

machine added with the FSM debugging feature.

f For coding guidelines for specifying FSM in Verilog and VHDL, refer to the

Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.

h For information about adding FSM signals to the configuration file, refer to Setting Up

the SignalTap II Logic Analyzer in Quartus II Help.

Figure 15–4. Decoded FSM Mnemonics

15–14 Chapter 15: Design Debugging Using the SignalTap II Logic Analyzer

Configure the SignalTap II Logic Analyzer

Quartus II Handbook Version 10.1 Volume 3: Verification December 2010 Altera Corporation

Modifying and Restoring Mnemonic Tables for State Machines

When you add FSM state signals via the FSM debugging feature, the SignalTap II

Logic Analyzer GUI creates a mnemonic table using the format

<StateSignalName>_

table

, where StateSignalName is the name of the state signals

that you have declared in your RTL. You can edit any mnemonic table using the

Mnemonic Table Setup dialog box.

If you want to restore a mnemonic table that was modified, right-click anywhere in

the node list window and select Recreate State Machine Mnemonics. By default,

restoring a mnemonic table overwrites the existing mnemonic table that you

modified. To restore a FSM mnemonic table to a new record, turn off Overwrite

existing mnemonic table in the Recreate State Machine Mnemonics dialog box.

1 If you have added or deleted a signal from the FSM state signal group from within the

setup tab, delete the modified register group and add the FSM signals back again.

For more information about using Mnemonics, refer to “Creating Mnemonics for Bit

Patterns” on page 15–59.

Additional Considerations

The SignalTap II configuration GUI recognizes state machines from your design only

if you use Quartus II Integrated Synthesis (QIS). The state machine debugging feature

is not able to track the FSM signals or state encoding if you use other EDA synthesis

tools.

If you add post-fit FSM signals, the SignalTap II Logic Analyzer FSM debug feature

may not track all optimization changes that are a part of the compilation process. If

the following two specific optimizations are enabled, the SignalTap II FSM debug

feature may not list mnemonic tables for state machines in the design:

■ If you have physical synthesis turned on, state registers may be resource balanced

(register retiming) to improve f

MAX

. The FSM debug feature does not list post-fit

FSM state registers if register retiming occurs.

■ The FSM debugging feature does not list state signals that have been packed into

RAM and DSP blocks during QIS or Fitter optimizations.

You can still use the FSM debugging feature to add pre-synthesis state signals.

Specifying the Sample Depth

The sample depth specifies the number of samples that are captured and stored for

each signal in the captured data buffer. To specify the sample depth, select the desired

number of samples to store in the Sample Depth list. The sample depth ranges from

0 to 128K.

If device memory resources are limited, you may not be able to successfully compile

your design with the sample buffer size you have selected. Try reducing the sample

depth to reduce resource usage.

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