TC358870XBG：超高速DSI-HDMI桥接器，支持4K@30fps视频转换

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TC358870XBG是一款专为移动设备设计的超高速DSI-HDMI桥接芯片，由东芝公司于2015年发布。这款芯片的主要功能是将高清（超过4 Gbps）的HDMI信号转换为MIPID（Mobile Interface Port Interface）接口的视频数据，以驱动新一代应用处理器驱动双DSI链路显示。它作为TC358779XBG的后续产品，取消了标量功能，专注于高带宽视频传输。该芯片的核心特性包括： 1. HDMI接收器接口： - 支持HDMI 1.4b标准，能够处理高达4K×2K分辨率、30fps的视频流，但不支持深度颜色（如10-bit或更深），仅支持最高24位每像素（bpp）的颜色深度。 - 支持多种颜色格式： - RGB: 24-bpp (例如RGB888) - YCbCr 444: 24-bpp - YCbCr 422: 24-bpp - 内置色彩转换能力：4:2:2到4:4:4和4:4:4到4:2:2之间可转换，以及RGB 888到YCbCr（4:4:4/4:2:2）和YCbCr（4:4:4/4:2:2）到RGB 888/666。 - 特殊情况下的支持：对于RGB666格式（R=G=B=8位），实际表示为R[5:0]=00, G[5:0]=00, B[5:0]=00）。 2. 音频支持： - 内置音频PLL（Phase-Locked Loop）提供音频频率合成，确保音频同步传输。 3. 性能参数： - 最大HDMI时钟速度：297 MHz，这决定了数据传输的速率上限，达到7.2 Gbps。 4. 设备连接需求： - 需要双链路MIPID接口，每条链路支持1 Gbps的数据带宽，以支持最大7.2 Gbps的视频数据传输。 TC358870XBG的设计使得移动设备能够轻松集成高分辨率显示和高速视频传输，对于现代智能手机、平板电脑等移动设备中的多媒体应用至关重要。使用这款芯片可以提高设备的显示性能，同时简化系统设计，减少额外的信号转换组件，提升整体系统效率。开发者在开发针对这类芯片的应用时，需要熟悉其接口规范、配置寄存器以及与之相关的驱动程序开发技术。

TC358870XBG

16 2015-02-02

Table of Figures

Figure 1.1 TC358870XBG System Overview .......................................................................................... 21

Figure 2.1 TC358870XBG 80-Pin Layout (Top View).............................................................................. 24

Figure 3.1 Block Diagram of TC358870XBG ........................................................................................... 25

Figure 3.2 Line Splitting for Dual DSI Link ............................................................................................... 28

Figure 3.3 Line Overlap Splitting in Dual DSI Link ................................................................................... 29

Figure 3.4 DSI Command Transmission Timing ...................................................................................... 30

Figure 3.5 DSI Short Command Packet Assembly .................................................................................. 31

Figure 3.6 DSI Long Command Packet Assembly .................................................................................. 32

Figure 3.7 Flow diagram for LPRX data reception using Register interface ........................................... 34

Figure 3.8 CEC reception overview ......................................................................................................... 35

Figure 3.9 CEC noise cancellation example ............................................................................................ 36

Figure 3.10 CEC start bit detection .......................................................................................................... 36

Figure 3.11 waveform error detection ...................................................................................................... 37

Figure 3.12 sampling time example ......................................................................................................... 37

Figure 3.13 CEC transmission example .................................................................................................. 38

Figure 3.14 Transmission starts ............................................................................................................... 38

Figure 3.15 Transmission timing .............................................................................................................. 39

Figure 3.16 Arbitration Error check .......................................................................................................... 39

Figure 3.17 CEC Block diagram............................................................................................................... 40

Figure 3.18 Data input timing of standard format (Sony format); L_ch=H, R_ch=L ................................ 42

Figure 3.19 Data input timing of Left-Justified format; L_ch=H, R_ch=L................................................. 42

Figure 3.20 Data input timing of I2S data format (Phillips format); L_ch=L, R_ch=H ............................. 43

Figure 3.21 HBR Audio stream over 1 I2S lane and four (4) I2S lanes ................................................... 44

Figure 3.22 I2S N-Channel TDM timing ................................................................................................... 45

Figure 3.23 NEC Configuration of Frame ................................................................................................ 46

Figure 3.24 NEC Bit Description .............................................................................................................. 46

Figure 3.25 NEC Frame Interval (Tf) ....................................................................................................... 46

Figure 3.26 Example of Lead Code min/max values for H and L detection ............................................ 47

Figure 3.27 Register Write Transfer over I

C Bus ................................................................................... 49

Figure 3.28 Random Register Read Transfer over I

C Bus .................................................................... 49

Figure 3.29 Continuous Register Read Transfer over I

C Bus ................................................................ 49

Figure 3.30 I

C Write Transfers Translated to Register Write Accesses ................................................ 50

Figure 3.31 I

C Read Transfers to Register Read Accesses .................................................................. 50

Figure 4.1 Power On Sequence ............................................................................................................... 54

Figure 4.2 Power Down Sequence .......................................................................................................... 55

Figure 6.1 TC358870XBG package (P-VFBGA80-0707-0.65-001) ...................................................... 294

Figure 9.1 D-PHY Signaling Levels .................................................................................................... 299

Figure 9.2 Input Glitch Rejection of Low-Power Receivers ................................................................... 302

Figure 9.3 Data to clock timing reference .............................................................................................. 302

Figure 9.4 I2S/TDM Timing Diagram ..................................................................................................... 303

Figure 10.1 Example of DDC I/F Connection ........................................................................................ 305

Figure 10.2 Connection of REXT resistance ......................................................................................... 306

Figure 10.3 Audio Clock External LPF circuit block diagram ................................................................. 306

Figure 10.4 Recommended power supply circuit with external switch .................................................. 307

Figure 10.5 Recommended power supply circuit with current protection regulator .............................. 308

Figure 10.6 Recommended power supply circuit at VDDIO18 = 3.3V .................................................. 309

TC358870XBG

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List of Tables

Table 2.1 TC358870XBG Functional Signal List ..................................................................................... 22

Table 2.2 BGA80 Pin Count Summary .................................................................................................... 24

Table 3.1 HDMI 3D Structure ................................................................................................................... 26

Table 3.2 InfoFrame Data Registers Summary ....................................................................................... 27

Table 4.1 Possible DSITX0/1_PLL parameters ....................................................................................... 53

Table 4.2 Power On Sequence Timing .................................................................................................... 54

Table 4.3 Power Down Sequence Timing................................................................................................ 55

Table 5.1 Global Register Map ................................................................................................................ 56

Table 5.2 CEC Enable Register ............................................................................................................. 136

Table 5.3 CEC Logical Address Register .............................................................................................. 137

Table 5.4 CEC Reset Register ............................................................................................................... 137

Table 5.5 CEC Receive Enable Register ............................................................................................... 138

Table 5.6 CEC Receive Control Register 1 ........................................................................................... 138

Table 5.7 CEC Receive Control Register 2 ........................................................................................... 140

Table 5.8 CEC Receive Control Register 3 ........................................................................................... 141

Table 5.9 CEC Transmit Enable Register .............................................................................................. 142

Table 5.10 CEC Transmit Control Register ........................................................................................... 143

Table 5.11 CEC Receive Interrupt Status Register ............................................................................... 144

Table 5.12 Interrupt Flag Register ......................................................................................................... 144

Table 5.13 CEC Receive Buffer Registers (01-16) ................................................................................ 145

Table 5.14 CEC Transmit Buffer Registers (01-16) ............................................................................... 145

Table 5.15 Interrupt Flag Register ......................................................................................................... 145

Table 5.16 CEC Interrupt Enable Register ............................................................................................ 146

Table 5.17 CEC Interrupt Enable Register ............................................................................................ 146

Table 6.1 Mechanical Dimension ........................................................................................................... 294

Table 11.1 Revision History ................................................................................................................... 310

TC358870XBG

19 2015-02-02

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