SiI9136 HDMI Deep Color Transmitter
Data Sheet
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10 SiI-DS-1075-B
3.1.1. Input Clock Multiplier/Divider
The input pixel clock can be multiplied by 0.5, 2 or 4. Video input formats which use a 2x clock (such as YC Mux mode)
can then be transmitted across the HDMI link with a 1x clock. Similarly, 1x-to-2x, 1x to-4x, and 2x-to-4x conversions are
possible.
3.1.2. Video Data Capture
The bus configurations support most standardized video input formats as well as other widely used non-standard
formats. Each configuration has four key attributes: data width, input mode, clock mode, and synchronization
attributes.
The video input port is a 36-bit wide bus that can be configured to any of the following data widths:
8-, 10- or 12-bit input in double-speed clock mode
12-, 15-, 18- or 24-bit input in dual-edge clock mode
16-, 20-, 24-, 30-, or 36-input in single-speed clock mode
The input mode includes color format (RGB, YCbCr, or xvYCC) and color sampling (4:4:4 or 4:2:2).
Clock mode refers to the input clock rate relative to the pixel clock rate. This device supports 1x mode, 2x mode, or
dual-edge mode. 1x mode and 2x mode means the input clock operates at one or two times the pixel clock rate. Dual-
edge mode means that the input clock rate equals the pixel clock rate, but a sample is captured on both the rising edge
and the falling edge of the input clock. Thus, with the Video Input configured for 24 bits with a dual-edge-clock, 48 bits
of video data are received per clock cycle. The 24 MSBs of the video data are latched on the first clock edge, and the 24
LSBs are latched on the next clock edge. The first clock edge is programmable and can be either the rising or the falling
edge.
Synchronization attributes refer to how the horizontal and vertical sync signals are configured. Separate
synchronization involves placing the horizontal sync, vertical sync, and data enable signals on separate input pins.
Embedded synchronization combines these signals with one or more of the data inputs.
3.1.3. Embedded Sync Decoder
The transmitter can create DE, HSYNC, and VSYNC signals using the start of active video (SAV) and end of active video
(EAV) codes within the ITU-R BT.656-format video stream.
3.1.4. Data Enable Generator
The transmitter includes logic to construct a Data Enable (DE) signal from the incoming HSYNC, VSYNC, and IDCK. This
signal is used to correct timing from sync extraction to conform to CEA-861D timing specifications. By programming
registers, the DE signal can define the size of the active display region. This feature is particularly useful when the
transmitter connects to MPEG decoders that do not provide a specific DE output signal.
3.1.5. Combiner
The clock, data, and sync information is combined into a complete set of signals required for TMDS encoding. From
here, the signals are manipulated by the register-selected video processing blocks.
3.1.6. 4:2:2 to 4:4:4 Upsampler
Chrominance upsampling and downsampling increase or decrease the number of chrominance samples in each line of
video. Upsampling doubles the number of chrominance samples in each line, converting 4:2:2 sampled video to 4:4:4
sampled video.
3.1.7. RGB Range Expansion
The SiI9334 transmitter can scale the input color range from limited-range into full-range using the range expansion
block. When enabled by itself, the range expansion block expands 16–235 (64–943 to 256–3775, 4096-60415 for
30/36/48-bit color depth) limited-range data into 0–255 (0–1023, 0–4095 to 0-65535 for 30/36/48-bit color depth) full-
range data for each video channel. When range expansion and the YCbCr to RGB color space converter are both
enabled, the input conversion range for the Cb and Cr channels is 16–240 (64–963, 256–3855 to 4096-61695 for
30/36/48-bit color depth).