W25Q128FVSIG：3V 128M位串行闪存技术规格详述

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"W25Q128FVSIG是一款3V的128M-位串行闪存，支持双通道SPI、四通道SPI和QPI接口的NOR FLASH存储器。这款芯片由旺宏电子（Winbond）生产，适用于各种需要高速数据存储的应用。产品规格书发布于2016年5月13日，提供了详细的芯片功能、封装类型和引脚配置等信息。" W25Q128FVSIG是旺宏电子推出的一款高密度串行闪存存储器，具备高速读取和灵活的数据传输模式。该芯片的主要特点包括： 1. **容量与电压**：提供128兆位（16MB）的存储容量，工作电压为3V。 2. **接口支持**：支持传统的串行外设接口（SPI）、双通道SPI、四通道SPI以及快速四通道接口（QPI），允许更快的数据传输速率。 3. **封装类型**：有多种封装形式，如SOIC/VSOP208-mil、WSON6x5-mm/8x6-mm、SOIC300-mil、TFBGA8x6-mm（5x5或6x4球阵列）和PDIP300-mil。 4. **引脚配置和描述**：包含了芯片选择（/CS）、串行数据输入/输出/IOs（DI, DO, IO0, IO1, IO2, IO3）、写保护（/WP）、保持（/HOLD）、串行时钟（CLK）和复位（/RESET）等关键引脚，每种封装的引脚配置和描述在规格书中都有详细列出。 5. **操作模式**：支持标准SPI指令、双通道SPI指令、四通道SPI指令、QPI指令，以及hold功能和软件控制的擦写操作。 6. **功能描述**：详细介绍了SPI/QPI操作的工作流程，包括不同模式下的指令集，如读取、写入、擦除等操作。这款存储器广泛应用于嵌入式系统、微控制器、消费类电子产品和工业设备中，因其小尺寸封装和高性能特性而受到青睐。用户可以根据其具体应用需求选择合适的封装形式和接口模式，实现高效的数据存储和访问。规格书中还涵盖了电气特性、操作条件、编程和擦除时间、温度范围等重要参数，为设计者提供了全面的技术参考。

W25Q128FV

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6.2 Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern, the

W25Q128FV provides several means to protect the data from inadvertent writes.

6.2.1 Write Protect Features

 Device resets when VCC is below threshold

 Time delay write disable after Power-up

 Write enable/disable instructions and automatic write disable after erase or program

 Software and Hardware (/WP pin) write protection using Status Registers

 Additional Individual Block/Sector Locks for array protection

 Write Protection using Power-down instruction

 Lock Down write protection for Status Register until the next power-up

 One Time Program (OTP) write protection for array and Security Registers using Status Register

* Note: This feature is available upon special order. Please contact Winbond for details.

Upon power-up or at power-down, the W25Q128FV will maintain a reset condition while VCC is below

the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all

operations are disabled and no instructions are recognized. During power-up and after the VCC voltage

exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW.

This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write

Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at

power-up until the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply

level at power-down to prevent adverse command sequence. If needed a pull-up resister on /CS can be

used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write

Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program,

Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After

completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared

to a write-disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting

the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP[2:0]) bits. These

settings allow a portion or the entire memory array to be configured as read only. Used in conjunction

with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under

hardware control. See Status Register section for further information. Additionally, the Power-down

instruction offers an extra level of write protection as all instructions are ignored except for the Release

Power-down instruction.

The W25Q128FV also provides another Write Protect method using the Individual Block Locks. Each

64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the

top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit

is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1,

Erase or Program commands issued to the corresponding sector or block will be ignored. When the

device is powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected

from Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any

specific sector or block.

The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When

WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas

of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.

W25Q128FV

Publication Release Date: May 13, 2016

- 16 - Revision M

7. STATUS AND CONFIGURATION REGISTERS

Three Status and Configuration Registers are provided for W25Q128FV. The Read Status Register-

1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether

the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register

lock status, Erase/Program Suspend status, output driver strength, power-up and current Address

Mode. The Write Status Register instruction can be used to configure the device write protection features,

Quad SPI setting, Security Register OTP locks, Hold/Reset functions, output driver strength and power-

up Address Mode. Write access to the Status Register is controlled by the state of the non-volatile Status

operations, the /WP pin.

7.1 Status Registers

S7 S6 S5 S4 S3 S2 S1 S0

SRP0 SEC TB BP2 BP1 BP0 WEL BUSY

Status Register Protect 0

(Volatile/Non-Volatile Writable)

Top/Bottom Protect Bit

(Volatile/Non-Volatile Writable)

Block Protect Bits

(Volatile/Non-Volatile Writable)

Write Enable Latch

(Status-Only)

Erase/Write In Progress

(Status-Only)

Sector Protect Bit

(Volatile/Non-Volatile Writable)

Figure 4a. Status Register-1

7.1.1 Erase/Write In Progress (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a

Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or

Erase/Program Security Register instruction. During this time the device will ignore further instructions

except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and

tCE in AC Characteristics). When the program, erase or write status/security register instruction has

completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.

7.1.2 Write Enable Latch (WEL) – Status Only

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a

Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write

disable state occurs upon power-up or after any of the following instructions: Write Disable, Page

Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase

Security Register and Program Security Register.

7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,

and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write

Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can

W25Q128FV

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be protected from Program and Erase instructions (see Status Register Memory Protection table). The

factory default setting for the Block Protection Bits is 0, none of the array protected.

7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the

Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.

The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction

depending on the state of the SRP0, SRP1 and WEL bits.

7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0)

protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of

the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.

7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used

in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection.

Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed.

For instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when

CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only.

Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register

(S8 and S7). The SRP bits control the method of write protection: software protection, hardware

protection, power supply lock-down or one time programmable (OTP) protection.

SRP1

SRP0

/WP

Status

Description

Software

Protection

/WP pin has no control. The Status register can be

written to after a Write Enable instruction, WEL=1.

[Factory Default]

Hardware

Protected

When /WP pin is low the Status Register locked and

cannot be written to.

Hardware

Unprotected

When /WP pin is high the Status register is unlocked

and can be written to after a Write Enable instruction,

WEL=1.

Power

Supply

Lock-Down

Status Register is protected and cannot be written to

again until the next power-down, power-up cycle.

(1)

One Time

Program

(2)

Status Register is permanently protected and cannot be

written to.

Notes:

1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available upon special order. Please contact Winbond for details.

W25Q128FV

Publication Release Date: May 13, 2016

- 18 - Revision M

S15 S14 S13 S12 S11 S10 S9 S8

SUS CMP LB3 LB2 LB1 (R) QE SRP1

Status Register Protect 1

(Volatile/Non-Volatile Writable)

Complement Protect

(Volatile/Non-Volatile Writable)

Security Register Lock Bits

(Volatile/Non-Volatile OTP Writable)

Reserved

Quad Enable

(Volatile/Non-Volatile Writable)

Suspend Status

(Status-Only)

Figure 4b. Status Register-2

7.1.8 Erase/Program Suspend Status (SUS) – Status Only

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a

Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program

Resume (7Ah) instruction as well as a power-down, power-up cycle.

7.1.9 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable

The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in

Status Register (S13, S12, S11) that provide the write protect control and status to the Security

Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1

individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once

it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI

and QPI operation. When the QE bit is set to a 0 state (factory default for part number with ordering

options “IG”,”IP” and “IF”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1(factory

default for Quad Enabled part numbers with ordering option “IQ”), the Quad IO2 and IO3 pins are

enabled, and /WP and /HOLD functions are disabled.

QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from

Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI

mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE

bit from a “1” to a “0”.

WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during

standard SPI or Dual SPI operation, the QE bit should never be set to a 1.

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