AFE5808A：集成式8通道超声波前端，低噪声与高精度

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TI-AFE5808A是一款高性能、全集成的8通道超声波模拟前端组件，专为医疗超声成像应用设计。该芯片具有以下主要特性： 1. 高分辨率模拟前端：AFE5808A提供1/16波长的相位分辨率，支持16X, 8X, 4X和1X CWClock（连续波混频器时钟）选择，能适应多种系统配置。 2. 低噪声放大器（LNA）：LNA具备可编程增益功能，最高可达24dB，能有效抑制3rd和5th谐波噪声，提供了12dB、18dB或12dB的不同增益设置，同时支持灵活的输入时钟源，包括0.25VPP、0.5VPP和1VPP的线性输入范围。 3. 全功能模块：包括电压控制大电流差分放大器(VCAT)、增益可编程放大器(PGA)、低通滤波器(LPF)以及高精度的14位或12位模数转换器(ADC)，内置了小型化的15mm x 9mm, 135引脚的非倒置球栅阵列(NFBGA)封装。 4. 信号处理能力：内置CWMixer（连续波混频器）和增益放大器，用于信号的高效处理和混合，支持1XCLK和1XCLK的时钟同步，输出CWI/QVout信号。 5. 超低噪声性能：在典型工作条件下，输入信噪比达到惊人的0.75nV/√Hz，对于噪声敏感的应用如医疗超声成像至关重要。 6. 节能设计：每个通道的功耗仅为158mW，有助于系统整体的能耗优化。 7. 灵活的输入阻抗和终端模式：支持可编程的主动终止，以适应不同的应用场景需求。该芯片的应用领域广泛，特别适合于对低噪声和高速度要求严格的医疗超声设备，如彩超、实时成像和诊断系统。此外，文档还提供了丰富的技术文档、工具与软件、支持服务以及社区资源，为用户提供了完整的开发支持。 TI-AFE5808A是一款在超声成像领域极具竞争力的产品，其高性能、低噪声和集成度高的特点使其成为医疗设备设计者们的理想选择。通过深入理解和利用这些特性，工程师可以构建出更高效、更精确的医疗超声解决方案。

AFE5808A

SLOS729D –OCTOBER 2011–REVISED NOVEMBER 2015

www.ti.com

Electrical Characteristics (continued)

At AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, ac-coupled with 0.1 µF at INP and bypassed to

ground with 15 nF at INM, no active termination, V

CNTL

= 0 V, f

= 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample

rate = 65 MSPS, LPF filter = 15 MHz, low-noise mode, V

OUT

= –1 dBFS, internal 500-Ω CW feedback resistor, CMOS CW

clocks, ADC configured in internal reference mode, single-ended VCNTL mode, VCNTLM = GND, at ambient temperature

= 25°C (unless otherwise noted). Min and max values are specified across full-temperature range with AVDD_5 V = 5 V,

AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V

PARAMETER TEST CONDITION MIN TYP MAX UNIT

ADC Power dissipation/CH 65 MSPS 59 69 mW/CH

50 MSPS 51

40 MSPS 46

20 MSPS 35

Power dissipation in power down mode PDN_VCA = high, PDN_ADC = high 25 mW/CH

Complete power-down, PDN_Global = high 0.6

Power-down response time Time taken to enter power down 1 µs

Power-up response time VCA power down 2µs+1% of PDN

time

µs

ADC power down 1

Complete power down 2.5 ms

= 5 MHz, at 50-mV

noise at 1 kHz on supply

(4)

–65 dBc

Power supply modulation ratio, AVDD and

AVDD_5V

= 5 MHz, at 50-mV

noise at 50 kHz on supply

(4)

–65 dBc

Power supply rejection ratio f = 10 kHz,VCNTL = 0 V (high gain), AVDD –40 dBc

f = 10 kHz,VCNTL = 0 V (high gain), AVDD_5V –55 dBc

f = 10 kHz,VCNTL = 1 V (low gain), AVDD –50 dBc

(4) PSMR specification is with respect to input signal amplitude.

Product Folder Links: AFE5808A

AFE5808A

SLOS729D –OCTOBER 2011–REVISED NOVEMBER 2015

www.ti.com

7.7 Switching Characteristics

Typical values are at 25°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, differential clock, C

LOAD

= 5

pF, R

LOAD

= 100 Ω, 14 bit, sample rate = 65MSPS (unless otherwise noted). Minimum and maximum values are across the

full temperature range T

MIN

= 0°C to T

MAX

= 85°C with AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V

(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ta The delay in time between the rising edge of the input sampling 0.7 3

Aperture delay ns

clock and the actual time at which the sampling occurs

Aperture delay Across channels within the same device ±150

matching

Aperture jitter 450 Fs rms

Default, after reset, or 0 x 2 [12] = 1, LOW_LATENCY = 1 11/8 Input

ADC latency clock

cycles

delay

Data and frame clock Input clock rising edge (zero cross) to frame clock rising edge (zero 3 5.4 7

delay cross) minus 3/7 of the input clock period (T).

Δt

delay

Delay variation At fixed supply and 20°C T difference. Device to device –1 1 ns

RISE

Data rise time Rise time measured from –100 to 100 mV, fall time measured from 0.14

100 mV to –100 mV, 10 MHz < f

CLKIN

< 65 MHz

FALL

Data fall time 0.15

FCLKRISE

Frame clock rise time Rise time measured from –100 mV to 100 mV, fall time measured 0.14

from 100 mV to –100 mV, 10 MHz < f

CLKIN

< 65 MHz

FCLKFALL

Frame clock fall time 0.15

Frame clock duty cycle Zero crossing of the rising edge to zero crossing of the falling edge 48% 50% 52%

DCLKRISE

Bit clock rise time Rise time measured from –100 to 100 mV, fall time measured from 0.13

100 mV to –100 mV, 10 MHz < f

CLKIN

< 65 MHz

DCLKFALL

Bit clock fall time 0.12

Zero crossing of the rising edge to zero crossing of the falling edge 46% 54%

Bit clock duty cycle

10 MHz < f

CLKIN

< 65 MHz

(1) Timing parameters are ensured by design and characterization; not production tested.

7.8 Timing Requirements

Minimum values across full temperature range T

MIN

= 0°C to T

MAX

= 85°C, AVDD_5V =5 V, AVDD = 3.3 V, AVDD_ADC = 1.8

V, DVDD = 1.8 V

PARAMETER DESCRIPTION MIN TYP MAX UNIT

SCLK period 50 ns

SCLK high time 20 ns

SCLK low time 20 ns

Data setup time 5 ns

Data hold time 5 ns

SEN fall to SCLK rise 8 ns

Time between last SCLK rising edge to SEN rising edge 8 ns

SDOUT delay 12 20 28 ns

Product Folder Links: AFE5808A

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