异步VLSI设计实战指南：低功耗高性能电路设计秘籍

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"《设计师指南：异步VLSI》是一本面向异步电路设计的实用手册，专为希望创建低功耗、高性能电路且缩短设计周期的工程师而编写。与传统的同步设计方法相比，它提供了一种实践性的替代方案，能够实现接近定制ASIC标准单元流程的性能，同时保持设计时间的商业可用性。本书深入探讨了异步设计的优势，包括设计权衡、具体的实例设计和章节末尾的练习题，旨在教授实际技巧和现实世界应用。它特别适合对替代设计风格和系统级芯片（SoC）感兴趣的电路设计学生，以及在工业界寻求解决老问题的新方法的设计师。作者彼得·A·比瑞尔（Peter A. Beerel），既是TimeLess Design Automation公司的首席执行官，这家公司专门商业化异步VLSI工具和库，也是南加州大学电气工程系的副教授。他拥有15年的异步VLSI研究和教学经验，曾多次获奖，其中包括VSoE杰出成就奖。书中他将丰富的专业知识融入实际案例，引导读者理解和掌握这一前沿领域的设计技术。通过阅读本书，读者不仅能提升异步电路设计的技能，还能了解到如何将这些理论应用于解决复杂的电子系统设计挑战。"

a wide variety of applications [45][46][47][48]. However, the mass application of

asynchronous design has been an elusive goal for academic researchers and, while

recent advances are pro mising, only time will tell whether this technology will take

a larger foothold in the very-large-scale integration (VLSI) world.

There are many different types of integrated circuits (ICs) and the design style

choice for a particular application depends on the relative performance, power,

volume, and other market demands of the device. For example, traditionally, low-

volume specialized products with only moderate power and performance require-

ments can use field programmable gate arrays (FPGAs), which provide reduced

time to market and low design risk, primarily because of their reprogrammable

nature. Higher-volume products with more aggressive power and performance

requirements often require application specific integrated circuits (ASICs), which

come at the cost of the increased design and verification effort associated with the

finalizing of the manufacturing process.

Products that require significant programmability may also contain some type

of microprocessor to enable software support. Products whi ch require significant

storage will contain large banks of on-chip memories. Both micro-processors and

memory blocks are available on modern FPGAs and can be integrated into an

ASIC in the form of intellectual property cores. In addition, dedicated chips for

memory are critical in complex system design and can store billions of bits of data

either in volatile or non-volatile forms.

Chips with high volumes, such as microprocessors, memory chips, and FPGAs,

may be able to support full-custom techniques with advanced circuit styles, such as

asynchronous design. In fact, asynchronous techniques have been used in memory

for years and a recent start-up is the commercializing of high-speed FPGAs, which

has been enabled by high-speed asynchronous circuits [42][43][48].

Most ASICs, however, rely on semi-custom techniques in which more con-

strained design styles are used. The relative simplicity of the constrained design

style enables the development of CAD tools that automate large portions of the

design process, significantly reducing design time. For asynchronous design to be

adopted for ASICs, existing CA D tool suites must be enhanced with scripts and

new tools to support asynchronous circuits. This chapter provides an overvie w of

the general issues that guide this design choice. In doing so, it identifies the

potential advantages of asynchronous design and the remaining challenges for

its widespread adoption.

1.1 Synchronous design basics

Synchronous design has been the dominant methodology since the 1960s. In

synchronous design, the system consists of sub-systems controlled by one or more

clocks that synchronize tasks and the communication between blocks. In tradi-

tional semi -custom synch ronous ASIC flows, co mbinational logic is placed in

between banks of flip-flops (FFs) that store the data, as shown in Figure 1.1.

2 Introduction

The combinational block must complete its operation within one clock cycle under

all possible input combinations, from all reachable states, in the worst-case operat-

ing environment. In this way, the clock ensures synchronization among combina-

tional blocks by guaranteeing that the output of every combinational block is valid

and ready to be stored before the next clock period begins. In fact, the data at the

inputs of the FFs may exhibit glitches or hazards, as long as they are guaranteed to

settle before the sampling clock edge arrives. In order to guarantee that the data is

stable when sampled, the clock period should account for the worst-case delay

including clock skew and all process variations.

Typical semi -custom design flows use a fixed set of library cells that have been

carefully designed, verified, an d characterized to support synthesis, placement,

routing, and post-layout verification tasks. This library is generally limited to

static CMOS gates, which, compared with more advanced dynamic logic families,

have higher noise margins and thus require far less analog verification. The cells

have accurate table-based characterization to support static timing and noise

analysis rather than more computationally intensive analog simulation. In par-

ticular, timing constraints are reduced to the setup and hold times on FFs, which

static timing analysis tools can verify reliably with minimal user input. This

constrained methodology has facilitated the development of mature suites of

CAD tools that yield relatively short, 12-month, design times.

Full-custom flows use more labor-intensive advanced design styles and less

automated tools to obtain higher performance and lower power. In particular,

full-custom ICs have clock frequencies that are three to eight times higher than

those for semi-custom flows, owing, to their advanced architectures, micro-

architectures, circuit styles, and manufacturing processes [4 ]. The differences

include: the use of advanced pipelining, clock-tree design, registers, dynamic logic,

and time borrowing; more careful logic design, cell design, wire sizing, floor-

planning, placement, and management of wires; the better management of process

variation; and, finally, accessibility to faster manufacturing processes.

Comb

logic

PI PO

Clk

Figure 1.1. Traditional synchronous ASIC, showing the combinational logic and flip-flop.

The primary inputs and outputs are denoted PI and PO.

31.1 Synchronous design basics

In particular, full-custom designs can use a variety of forms of dynamic logic

which offer significant improvements in performance and power consumption [1]

[3][6]–[8]. For example, the application of dynamic logic in the IBM 1.0 GHz

design yields 50% to 100% higher performance compared with its static logic

equivalent [8]. In addition, advanced FFs and latches can reduce the overhead

associated with c lock skew and latch delays [7]. Moreover, latch delays can even

be removed by means of multiple overlapping clocks and dynamic logic, in a

widely used technique recently named skew-tolerant domino logic [6].

However, dynamic logic has lower noise margins than its static counterpart.

Dynamic logic is also more difficult to characterize using table-based methods ,

and static timing analysis tools tend to have less accurate results for such circuits

[3]. Consequently, more careful analog-level noise and timing verification is

required. Managing this verif ication, along with the other more manual aspects

of full-custom design, typically results in a significant increase in design time.

1.2 Challenges in synchronous design

Synchronous design has been the predominant design methodology largely because

of the simplicity and efficiency provided by the global clock. The registers decom-

pose the design into acyclic islands of combinational logic which facilitate efficient

design, synthesis, and analysis algorithms. However, the global nature of the clock

also leads to increasing design and automation challenges. In particular, the time-to-

market advantage of standard-cell-based ASIC designs is being subverted by the

increasingly difficult design challenges posed by modern semiconductor processes

[4]. These challenges affect both high-performance and low-power ASICs, as

described below.

1.2.1 Computer-aided design for high-performance

In earlier submicron designs, architecture, logic, and technology-mapping design

could proceed before and somewhat independently from the placement and

routing of the cells, power grid, and clocks because wire delays were negligible

compared with gate delays. In deep-submicron design, however, interconnect has

not scaled to the same degree as gates, and cross-talk between wires leads to

substantial changes in wire delay. Consequently, wire delay increasingly accounts

for a larger fraction of the critical path. In particular, the delays of long-range

wires may account for up to 70% of the critical path of some high-performance

designs [36]. This change in relative importance has caused the traditional separ-

ation of logic synthesis and physical design tasks to break down, because synthesis

cannot now properly account for the actual wire delays and other geometrical

effects. Since the late 1990s, this timing-closure problem and disconnect between

synthesis and physical design has forced numerous shipment schedules to slip.

4 Introduction

As a consequence, tighter integration of these CAD tools has been developed

and a wide range of post-placement optimization, including gate resizing,

buffer insertion, and wire width optimization, have become an essential part

of CAD tool suites. In addition, sophisticated cross-talk analysis techniques

that account for the switching window of various wires have been developed to

determine the impact in delay associated with increasingly large cross-coupling

capacitances. Understanding the impact of c ross-talk during post-placement

optimization is computationally challenging owing to the inherent feedback

between a cc urat e cross-talk anal ysis and post-placement optimizations. For

example, switching windows can shift dramatically owing to buffer insertion,

resulting in significant changes in the delay of neighboring wires. This computa-

tional challenge forces CAD tools to rely on approximations that yield non-

optimal designs.

Despite the co ntinued advances of modern CAD tools, the overall impact of

these challenges has been an increasingly large performance gap between full -

custom integrated circuits (ICs) and semi-custom ASICs. Moreover, it is predicted

that high-perform ance semi-custom designs will remain three times slower than

their full-custom counterparts despite all the potential advances in CAD tools [ 4 ].

In particular, conventional wisdom suggests that semi-custom CAD tools may

never support dynami c logic because of the added complexity of noise and timing

constraints and the lack of dynamic cell libraries.

1.2.2 Computer-aided design for low-power devices

As manufacturing feature sizes have decreased, transistors have become increas-

ingly leaky and power budgets have become increasingly difficult to meet. This has

motivated a range of improvements to the low-power ASIC flow. In particular,

low-leakage power-efficient cell design, multiple supply voltages on a single die,

gated power supplies, and more advanced clock-gating techniques are continually

being developed and incorporated in ASIC flows. In addition, a few full-custom

techniques for low power have also been explored and are just emerging in ASIC

tools; these techniques include low-voltage swings for long-range wires. However,

these low-swing circuits have reduced noise margins, which necessitates careful

wire planning, shielding, and some analog verification. Moreover, it is well known

that low-power latches can be used instead of flip-flops to reduce clock-tree

capacitance.

1.3 Asynchronous design basics

As a result of the increasing limitations and growing complexity of semi-custom

synchronous design, asynchronous circui ts are gaini ng in interest. In the absence

of a global clock that controls register and state updating, asynchronous designs

rely on handshaking to transfer data between functional blocks. One common way

51.3 Asynchronous design basics

to design asynchronous circuits is to organize the data transfer in channels that

group a bundle of data wires using handshaking signals. The channels are uni-

directional and typically point-to-point; they are represented as arrows in Figure 1.2.

Notice that the bi-directional communication of data between blocks A and

B requires two channels in opposite directions.

Many different design styles have been proposed for asynchronous circuits.

They differ in the method in which data is encoded in channels, the handshaking

protocol, and the number and type of timing assumptions required for the designs

to work properly. These different design tradeoffs make it difficult to make

general statements regarding the relative merits of the various benefits typically

associated with asynchronous design. In particular, some design styles yield low

power but are best suited for low-performance applications. Others yield high

performance at the expense of more power and additional timing assumptions.

All, however, provide a rigorous framework for exploring alternatives to syn-

chronous design.

1.4 Asynchronous design flows

There are many different possible design flows for asynchronous circuits. Here we

describe three, to demonstrate the diversity of flows being explored.

The first of these design flows is called refinement and involves the decom-

position of asynchronous blocks into a hi erarchical networ k of leaf cells,wherea

leaf cell is the smallest block that communicates with its neighbors via chann els.

Each leaf cell is typically implemented with a small se t of trans istors, typically

between 10 and 100. Early attempts to automate this process are encouraging,

but as of today industry relies on sign ifica nt m anual effort and a large re-usable

libr ary of macro ce lls (functional bloc ks, registers, and c rossbars) and leaf cells.

This technique was pioneered by Alain Martin at Caltech and has been applied

to several asynchronous microprocessors [9] a nd digital-signal processing

chips [25] . It has been commercial ized by Fulcrum Microsystems and has led

A B

C D

Figure 1.2. Asynchronous blocks communicating using channels.

6 Introduction

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