Supporting CUDA for an extended RISC-V GPU architecture
Ruobing Han
hanruobing@gatech.edu
Georgia Institute of Technology
USA
Blaise Tine
blaisetine@gatech.edu
Georgia Institute of Technology
USA
Jaewon Lee
jaewon.lee@gatech.edu
Georgia Institute of Technology
USA
Jaewoong Sim
jaewoong@snu.ac.kr
Seoul National University
Korea
Hyesoon Kim
hyesoon@cc.gatech.edu
Georgia Institute of Technology
USA
ABSTRACT
With the rapid development of scientic computation, more and
more researchers and developers are committed to implementing
various workloads/operations on dierent devices. Among all these
devices, NVIDIA GPU is the most popular choice due to its compre-
hensive documentation and excellent development tools. As a result,
there are abundant resources for hand-writing high-performance
CUDA codes. However, CUDA is mainly supported by only com-
mercial products and there has been no support for open-source
H/W platforms. RISC-V is the most popular choice for hardware
ISA, thanks to its elegant design and open-source license. In this
project, we aim to utilize these existing CUDA codes with RISC-V
devices. More specically, we design and implement a pipeline that
can execute CUDA source code on an RISC-V GPU architecture. We
have succeeded in executing CUDA kernels with several important
features, like multi-thread and atomic instructions, on an RISC-V
GPU architecture.
KEYWORDS
CUDA, RISC-V, Code Migration
ACM Reference Format:
Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, and Hyesoon Kim.
2021. Supporting CUDA for an extended RISC-V GPU architecture . In
Proceedings of ACM Conference (Conference’17). ACM, New York, NY, USA,
7 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
1 INTRODUCTION
RISC-V is the most popular choice for researchers in the aca-
demic community and engineers in hardware companies. The most
important reason is its open-source spirit. These open-source li-
censes encourage many researchers to devote themselves to the
development of a mature ecology for RISC-V, and thus, in turn,
more and more people are willing to join the community, as there
are existing fancy codes, hardware designs, and so on.
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https://doi.org/10.1145/nnnnnnn.nnnnnnn
In the RISC-V ecology, the software support is the bottleneck for
the blooming of the RISC-V community. Although OpenCL is an
open platform for heterogeneous computing, due to the stability and
software tool chain support, CUDA has been used widely. Unfortu-
nately, CUDA source code can only be compiled and then executed
on NVIDIA’s devices, which is a major obstacle to using RISC-V for a
wide range of applications, especially high-performance computing
and machine learning workloads.
One way to solve this dilemma is to use code migration[
8
,
10
,
13
].
Instead of using the default method to compile CUDA source code
with NVIDIA’s compiler, some researchers try to parse and modify
the source code to other high-level languages; more detail is shown
in Sec. 2.1. However, because these methods highly rely on the high
similarity between CUDA and the target high-level languages, they
are not general solutions. Another solution is to build a compiler
that directly compiles high-level CUDA language into a low-level
RISC-V binary le. To the best of our knowledge, although there
are translators that support generating RISC-V, none of them can
handle CUDA source code.
Thus, in this project we propose and build a pipeline to support
an end-to-end CUDA migration: the pipeline accepts CUDA source
codes as input and executes them on an extended RISC-V GPU
architecture. Our pipeline consists of several steps: translates CUDA
source code into NVVM IR[
4
], converts NVVM IR into SPIR-V IR
[
7
], forwards SPIR-V IR into POCL[
5
] to get RISC-V binary le,
and nally executes the binary le on an extended RISC-V GPU
architecture. We choose to use an intermediate representation (SPIR-
V) for two reasons 1) RISC-V is still in development and has a lot of
extensions, so we should not directly convert CUDA into RISC-V,
as it will make supporting new features in the future dicult for
our pipeline; 2) we want to make our pipeline more general so that
we can support CUDA as front-end and RISC-V as back-end. Our
pipeline is represented by Fig. 1.
In conclusion, the main contributions of our paper include the
following:
•
propose and implement a pipeline for executing CUDA source
code on RISC-V GPU;
•
build a translator support translating from NVVM to SPIR-
V
1
;
•
pipeline that is easy to maintain and further support other
front-end languages and back-end devices.
1
https://github.com/gthparch/NVPTX-SPIRV-Translator
arXiv:2109.00673v1 [cs.PL] 2 Sep 2021
用cuda kernel实现了几个feature:multi-thread
atomic instructions
IR: intermediate representation
portable open-source implementation