LM3S811微控制器datasheet学习指南

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LM3S811是一款由Texas Instruments（TI）公司生产的Stellaris系列微控制器。这是一份详细的LM3S811微控制器的数据手册，提供了关于该产品的全面技术规格、特性以及操作指南。作为一款基于ARM Cortex-M3内核的低功耗微控制器，LM3S811旨在满足工业级应用对高性能、灵活性和可靠性的需求。该文档涵盖了LM3S811的核心功能，包括但不限于： 1. **硬件架构**：介绍微控制器的硬件设计，包括处理器、内存、存储器、外设接口（如UART、SPI、I2C、GPIO等）、以及可能的加密和安全特性。 2. **性能参数**：阐述处理器的工作频率、引脚数量、功耗模式（睡眠、待机、运行等），以及能处理的运算速度和数据吞吐量。 3. **供电与电压范围**：数据手册会详细说明LM3S811支持的电源电压范围，以及相应的电流消耗情况。 4. **特性与功能**：如数字信号处理能力、低功耗模式、嵌入式系统功能（如看门狗定时器、实时时钟、中断系统等）、以及针对工业应用的特定增强功能。 5. **编程和调试**：提供软件开发工具链的信息，如Keil uVision、 iar EWARM等，以及连接方式（JTAG或SWD）。 6. **安全性和认证**：提及产品的安全特性，如AES加密、安全启动选项，以及符合的工业标准和法规要求。 7. **生产与保修**：强调生产数据的更新日期，并说明产品符合TI的标准保修政策，但并不一定包含所有参数的测试。 8. **警告和注意事项**：可能包含关于产品可用性、不适用于某些特定应用场合、以及使用过程中需注意的潜在问题和限制。 9. **联系信息**：文档末尾提供了TI公司的地址、网站以及技术支持的相关链接，便于用户获取更多帮助和支持。这份LM3S811资料副本是深入学习和开发基于LM3S811微控制器项目的重要参考资料，无论是硬件工程师、软件开发者还是系统集成者，都能从中找到所需的设计指导和技术细节。

Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 282

Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 285

Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 289

Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 299

Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 300

Watchdog Timer ........................................................................................................................... 301

Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 305

Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 306

Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 307

Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 308

Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 311

Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 312

Analog-to-Digital Converter (ADC) ............................................................................................. 325

Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 335

Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 336

Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 338

Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 343

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Table of Contents

Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 361

Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 368

Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 372

Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 376

Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 378

Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 382

Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 384

Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 386

Synchronous Serial Interface (SSI) ............................................................................................ 400

Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 412

Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 414

Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 416

Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 417

Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 419

Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 420

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Stellaris® LM3S811 Microcontroller

Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 422

Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 423

Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 424

Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 425

Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 426

Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 427

Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 428

Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 429

Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 430

Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 431

Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 432

Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 433

Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 434

Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 435

Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 436

Inter-Integrated Circuit (I

C) Interface ........................................................................................ 437

C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 452

C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 453

C Master Data (I2CMDR), offset 0x008 ......................................................................... 457

C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 458

C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 459

C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 460

C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 461

C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 462

C Master Configuration (I2CMCR), offset 0x020 ............................................................ 463

C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 465

C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 466

C Slave Data (I2CSDR), offset 0x808 ........................................................................... 468

C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 469

C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 470

C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 471

C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 472

Analog Comparator ..................................................................................................................... 473

Pulse Width Modulator (PWM) .................................................................................................... 484

Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 493

Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 497

Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 498

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Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 501

Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 502

Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 502

Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 502

Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 509

Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 509

Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 509

19January 09, 2011

Texas Instruments-Production Data

Stellaris® LM3S811 Microcontroller

Revision History

The revision history table notes changes made between the indicated revisions of the LM3S811

data sheet.

Table 1. Revision History

DescriptionRevisionDate

■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ

to SYSRESREQ.

■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register.

■ Added "Reset Sources" table to System Control chapter.

■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.

■ Added note that specific module clocks must be enabled before that module's registers can be

programmed. There must be a delay of 3 system clocks after the module clock is enabled before

any of that module's registers are accessed.

■ Changed I

C slave register base addresses and offsets to be relative to the I

C module base address

of 0x4002.0000 , so register bases and offsets were changed for all I

C slave registers. Note that

the hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x4002.0800 for the I

slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that

StellarisWare uses the old slave base address for these offsets.

■ Corrected nonlinearity and offset error parameters (E

, E

and E

) in ADC Characteristics table.

■ Added specification for maximum input voltage on a non-power pin when the microcontroller is

unpowered (V

NON

parameter in Maximum Ratings table).

■ Additional minor data sheet clarifications and corrections.

9102January 2011

■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two

new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was

added, including all the Cortex-M3 registers.

■ Changed register names to be consistent with StellarisWare

names: the Cortex-M3 Interrupt

Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and

the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0)

■ Added clarification of instruction execution during Flash operations.

■ Modified Figure 7-2 on page 228 to clarify operation of the GPIO inputs when used as an alternate

function.

■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes

the JTAG controller to be reset, resulting in a loss of JTAG communication.

■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.

■ Added missing table "Connections for Unused Signals" (Table 17-5 on page 530).

■ In Electrical Characteristics chapter:

– Added I

LKG

parameter (GPIO input leakage current) to Table 19-4 on page 534.

– Corrected values for t

CLKRF

parameter (SSIClk rise/fall time) in Table 19-16 on page 542.

■ Added dimensions for Tray and Tape and Reel shipping mediums.

7783September 2010

January 09, 201120

Texas Instruments-Production Data

Revision History

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