优化Virtex-5 FPGA的LUT与IP块打包策略

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本文主要探讨了针对Xilinx Virtex-5 FPGA的布线技术，这是一种关键步骤，它贯穿于综合、映射技术和放置流程之间。在商业FPGA设计中，有效的布线对电路速度、密度和功耗有重大影响。Virtex-5 FPGA集成了基于查找表（LUT）的逻辑块以及大型知识产权（IP）模块，如块RAM和数字信号处理器（DSP）。文章首先介绍了Virtex-5 FPGA的特点，其逻辑块包含双输出的6输入LUT，这使得它们能够执行最多6个输入的单个逻辑功能，或者不超过5个独特输入的两个逻辑函数。然而，第二个LUT输出的速度较低，因此在设计时需要谨慎使用。作者提出了针对双输出LUT的布线技术，这些技术旨在提高面积效率，同时最大限度地减少性能损失。接下来，文章详细讨论了如何针对大型IP块进行布线优化。对于块RAM，通过利用Virtex-5特有的布局和架构，设计者可以高效地将电路打包，从而提升设计性能。同样，对于DSP，有效的布线策略有助于最大化这些高性能单元的利用率，同时保持整体设计的效能平衡。通过深入研究这些特定技术，本文提供了一套适用于Virtex-5 FPGA的实用布线方法，帮助设计者在满足速度、密度和功耗要求的同时，优化电路设计的效率。理解并应用这些技术对于任何使用Virtex-5 FPGA进行设计的专业人士来说都是至关重要的，因为它们直接影响到最终产品的性能和成本。

Packing Techniques for Virtex-5 FPGAs · 18: 5

Fig. 2. Virtex-5 CLB and SLICE.

2.2.1 Logic Blocks. Logic blocks in Virtex-5 are called conﬁgurable logic

blocks (CLBs) and comprise two SLICEs and a switch matrix, as shown in

Figure 2. The switch matrix serves the purpose o f p roviding intra and inter-

CLB connectivity. As shown in the ﬁgure, each SLICE contains four 6-input

LUTs and 4 ﬂip-ﬂops. SLICEs receive and produce carry signals from neigh-

boring SLICEs for implementing fast ripple-carry addition.

Figure 3 zooms in on the details of portion of a SLICE—the LUT/ﬂip-ﬂop

pair. Dashed lines in the ﬁgure represent connections whose details are omit-

ted for clarity, but will be described below. Traditional LUTs in FPGAs have

a single output and can implement a single logic function. However, LUTs in

Virtex-5 FPGAs have two outputs, O5andO6, and can implement two logic

functions. Speciﬁcally, the LUT can implement a single logic function using up

to 6 inputs, with the output signal appearing on O6.TheLUTcanalsoimple-

ment two functions that together use up to 5 inputs, in which case, both the

O5andO6 outputs are used, and the LUT input A6mustbetiedtologic-1.

The architecture necessitates that when two LUT o utputs are used, only one

of them can be registered.

An important property of the LUT/FF structure in Figure 3 is that O6di-

rectly drives a SLICE output, A,whereasO5 must pass through an additional

multiplexer before reaching SLICE output, AMUX. This makes output O5

slower than output O6. Consequently, for high performance, O5 should not

be used in timing-critical combinational paths. The relative slowness of O5is

something that must be considered when packing LUTs into Virtex-5 SLICEs,

if high speed performance is to be maintained.

Figure 4 shows the dual-output LUT hardware implementation. LUTs in

FPGAs are implemented with trees of multiplexers, and the ﬁgure shows a

portion of a 6-input LUT. Values in SRAMs cells (on the left of the ﬁgure) are

set to hold the truth table for the logic function(s) implemented in the LUT.

The fastest LUT input, A6, is held constant at logic-1 when two functions are

mapped to the LUT, and therefore the fast input is unavailable for either of the

ACM Transactions on Reconﬁgurable Technology and Systems, Vol. 2, No. 3, Article 18, Pub. date: September 2009.

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优化Virtex-5 FPGA的LUT与IP块打包策略

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