TI DS90UB947-Q1：1080p60 FPD-Link III串行器技术规格

需积分: 9 151 浏览量更新于2024-06-27 4 收藏 2.46MB PDF 举报

TI的DS90UB947-Q1是一款专为FPD-Link III接口设计的高性能串行器，它旨在满足汽车行业严苛的AEC-Q100标准，适用于温度范围广泛(-40°C至+105°C)的环境。这款产品具有两个主要功能：FPD-Link III信号的发送和OpenLDI (LVDS)信号的接收。 DS90UB947-Q1的主要特性包括： 1. **高速数据传输能力**：支持双路FPD-Link III传输，每路可达到3Gbps的速率，单路最高可达96MHz的像素时钟，这对于WUXGA（1920x1200）和1080p60分辨率以及24位色深的图形处理非常适用。 2. **兼容性和灵活性**：支持170MHz的时钟频率，适应高分辨率显示需求。同时，提供了单通道和双通道的OpenLDI接收器，可以配置为18位RGB或24位RGB模式，以适应不同显示器的需求。 3. **AEC-Q100标准支持**：针对汽车应用，器件通过了AEC-Q100标准，确保在严苛的车内环境下可靠工作。 4. **反向通道支持**：内置高速反向通道，能够处理高达2Mbps的数据传输，这有助于实时通信和数据交换。 5. **供电选项**：VDDIO电压支持1.8V或3.3V，I2C接口电压为1.2V、3.3V和1.8V，确保与多种系统电源兼容。 6. **接口配置**：包括多个数据线（D0+/-, D1+/-, D2+/-, ... , D7+/-）和时钟线（CLK+/-, CLK2+/-），用于连接到显示设备或图形处理器。为了获取最新的技术规格和详细信息，建议查阅英文数据手册SNLS454以及TI官网www.ti.com上最新的版本，因为官方文档始终是最准确的来源。在进行实际设计时，务必参照英文文档，以确保设计的准确性和有效性。同时，TI还提供了技术支持、工具软件、文档和技术社区的支持，以便用户在使用过程中获得帮助。

DS90UB947-Q1

ZHCSD36A –NOVEMBER 2014–REVISED MARCH 2019

www.ti.com.cn

6.10 Typical Characteristics

Figure 10. Serializer Output at 2.975 Gbps (85-MHz

OpenLDI Clock)

Figure 11. Serializer Output at 3.36 Gbps (96-MHz OpenLDI

Clock)

I2C

Interface

I2C

PAT

GEN

Open-LDI

OLDI

Interface

Open LDI

Analog

Regs

Clocks

DFT

Audio

I2S

FPD3 TX

Analog

FPD-Link III

FPD3 TX

Analog

FPD-Link III

FPD-Link III TX

Digital

FPD-Link III TX

Digital

FPD3

Output

Select

Config

Single/Dual

Control

DS90UB947-Q1

www.ti.com.cn

ZHCSD36A –NOVEMBER 2014–REVISED MARCH 2019

7 Detailed Description

7.1 Overview

The DS90UB947-Q1 converts a single or dual FPD-Link (Open LDI) interface (up to 8 LVDS lanes + 1 clock) to

an FPD-Link III interface. This device transmits a 35-bit symbol over a single serial pair operating up to 3.36Gbps

line rate, or two serial pairs operating up to 2.975Gbps line rate. The serial stream contains an embedded clock,

video control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal quality

and support AC coupling.

The DS90UB947-Q1 serializer is intended for use with a DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB940-Q1,

DS90UB948-Q1 deserializer.

The DS90UB947-Q1 serializer and companion deserializer incorporate an I2C compatible interface. The I2C

compatible interface allows programming of serializer or deserializer devices from a local host controller. In

addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between

serializer/deserializer as well as remote I2C slave devices.

The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward

channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to

serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial

link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at

either side of the serial link.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 High-Speed Forward Channel Data Transfer

The High-Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, I2C,

GPIOs, and I2S audio transmitted from serializer to deserializer. Figure 12 shows the serial stream per clock

cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,

balanced and scrambled.

Figure 12. FPD-Link III Serial Stream

DS90UB947-Q1

ZHCSD36A –NOVEMBER 2014–REVISED MARCH 2019

www.ti.com.cn

Feature Description (continued)

The device supports OpenLDI clocks in the range of 25 MHz to 96 MHz over one lane, or 50 MHz to 170 MHz

over two lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum) , or 2.975 Gbps

maximum per lane (875 Mbps minimum) when transmitting over both lanes.

7.3.2 Back Channel Data Transfer

The Backward Channel provides bidirectional communication between the display and host processor. The

information is carried from the deserializer to the serializer as serial frames. The back channel control data is

transferred over both serial links along with the high-speed forward data, DC balance coding and embedded

clock information. This architecture provides a backward path across the serial link together with a high-speed

forward channel. The back channel contains the I2C, CRC and 4 bits of standard GPIO information with 5, 10, or

20 Mbps line rate (configured by the compatible deserializer).

7.3.3 FPD-Link III Port Register Access

The DS90UB947-Q1 contains two downstream ports, therefore some registers must be duplicated to allow

control and monitoring of the two ports. To facilitate this, a TX_PORT_SEL register controls access to the two

sets of registers. Registers that are shared between ports (not duplicated) will be available independent of the

settings in the TX_PORT_SEL register.

Setting the TX_PORT0_SEL or TX_PORT1_SEL bit will allow a read of the register for the selected port. If both

bits are set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing

simultaneous writes to both ports if both select bits are set.

Setting the PORT1_I2C_EN bit will enable a second I

C slave address, allowing access to the second port

registers through the second I

C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be

ignored.

7.3.4 OpenLDI Input Frame and Color Bit Mapping Select

The DS90UB947-Q1 can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes,

shown in Figure 13 and Figure 14. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock

input to CLK± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock

periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL strap option or

by Register (Table 10).

剩余83页未读，继续阅读

不觉明了

粉丝: 3967
资源: 5759

TI DS90UB947-Q1：1080p60 FPD-Link III串行器技术规格

TI-DS90UB947N-Q1.pdf

TI-DS90UH941AS-Q1.pdf

TI-DS90UB921-Q1.pdf

TI-DS90UB949A-Q1.pdf

TI-DS90UB925Q-Q1.pdf

TI-DS90UB904Q-Q1.pdf

TI-DS90UB928Q-Q1.pdf

TI-DS90UB902Q-Q1.pdf

TI-DS90UB914A-Q1.pdf

TI-DS90UB927Q-Q1.pdf

最新资源