全数字锁相环在电网电压相位检测中的应用研究

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"这篇研究论文探讨了一种全数字锁相环(ADPLL)在电网电压相位检测中的建模与实现。该ADPLL具有宽跟踪范围和快速捕捉时间，并能低成本地集成到数字控制器中。文章通过分析ADPLL的工作原理建立了其在线数学模型，并对其线性化模型进行了分析，以评估由于非线性和离散特性导致的稳态和动态性能。与传统DPLL相比，提出的ADPLL在输入信号频率偏离中心频率时几乎无稳态相位误差，且跟踪速度显著提高。" 在电力系统中，准确检测电网电压的相位至关重要，因为这直接影响到电力系统的稳定运行和电能质量。全数字锁相环(ADPLL)作为一种相位检测技术，在电力应用中表现出许多优势。本研究提出的新颖ADPLL设计针对电网电压相位检测，其关键特性包括： 1. **宽跟踪范围**：ADPLL能够跟踪输入信号在较宽频率范围内的相位变化，这意味着它能够适应电网频率的波动，保持对电压波形的精确同步。 2. **快速捕捉时间**：快速的捕捉能力使得ADPLL能够在短时间内锁定到输入信号的相位，这对于快速响应电网状态变化至关重要。 3. **低成本集成**：该ADPLL设计易于整合到数字控制系统中，降低了硬件成本和复杂性，有利于实现智能化和数字化的电力系统。 4. **线性化模型与性能评估**：论文通过分析ADPLL的工作原理，建立了数学模型，然后进行线性化处理，以评估在非线性和离散特性影响下的系统性能。这有助于理解系统在不同条件下的行为并优化设计。 5. **低稳态相位误差**：与传统的数字锁相环(DPLL)相比，该ADPLL在输入信号频率偏离中心频率时，能够保持极小的相位误差，提高了检测精度。 6. **高速跟踪能力**：论文指出，提出的ADPLL在相位跟踪速度上显著优于其他ADPLL设计，这在需要快速响应的电力应用场景中尤其重要，例如在电网频率漂移或扰动的情况下。这项研究为电网电压相位检测提供了一个高性能、低成本的解决方案，对于提高电力系统的自动化水平和应对电网异常情况的能力具有重要意义。通过理论建模和实验证明，这种ADPLL设计有可能成为未来智能电网中不可或缺的一部分。

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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 0, NO. 0, 2012 1

Modeling and Implementation of an All Digital

Phase-Locked-Loop for Grid-Voltage Phase Detection

Hua Geng, Member, IEEE, Jianbo Sun, Shuai Xiao, Student Member, IEEE, and Geng Yang, Senior Member, IEEE

Abstract—In this paper, a novel all digital phase-locked-loop

(ADPLL) is proposed for the phase detection of power grid

voltage. The proposed ADPLL features wide track-in range and

fast pull-in time, and it can be e asily integrated into the digital

controller with low cost. The nonlinear model of such digital

system is derived from the operation principle of the ADPLL and

the linearized model is then obtained to evaluate the steady and

dynamic performance due to the nonlinear and discrete property.

Compared with the conventional DPLL, the proposed ADPLL has

almost no steady state phase error when the frequency of the input

signal deviates from the center frequency. Moreover, the tracking

speed is highly improved. In contrast with other AD PLLs, the

proposed one employs the loop ﬁlter with proportional-Integral

(PI) structure, which can help to eliminate the steady state error

excited by high-order disturbancesornoise.Asaresult,alow

system clock or sampling frequency is enough to get a satisfactory

performance, which is an attractive advantage for the low cost ap-

plications. Simulation and experimental results verify the analysis

and the effectiveness of the ADPLL.

Index Terms—All digital phase-locked-loop (ADPLL), digital

system modeling, phase detection.

I. INTRODUCTION

HASE-LOCKED LO OP (PLL) technique has contributed

signiﬁcantly toward the advancement in power converter

based control s ystem s since the 1970s [1]–[3]. In the motor

servo control system, PLL can be employed to track the rotor

position according to the resolver signals [1]. In the grid-con-

nected power conversion systems, such as wind energy con-

version system (WECS) [4] or ﬂexible ac transmission system

(FACTS) [5], PLL is crucial to extract the frequency and angle

information of the utility voltage for the s ynchronization of the

inverter ou tput voltages [6].

Manuscript received October 27, 2011; revised January 16, 2012, May 01,

2012, and June 20, 2012; accepted July 09, 2012. Date of publication July 20,

2012; date of current version nulldate. This work was sponsored by National

Natural Science Foundation of China (61104046), Tsinghua University Initia-

tive Scientiﬁc Research Program and grants from the Power Electronics Science

and Education Development Program of Delta Environmental & Educational

Foundation. Paper no. TII-11-679.

H. Geng, S . Xiao and G. Yang are with Automation Department, Tsinghua

University, Beijing 100081, China (e-mail: geng hua@tsinghua.edu .cn; xi-

aoshuai1000@126.com; yanggeng@tsinghua.edu.cn).

J. Sun was with Automation Department, Tsinghua University, Bei-

jing 100081, Chin a. He is now w ith the Departmen t o f Electrical Engi-

neering, Univer sity of California, Lo s Angeles, CA 90 095 USA (e-m ail:

jsun.thu@gmail.com).

Color versions of one or more of the ﬁgures in this paper are available online

at http://ieeexplore.i eee.org.

Dig

ital Object Identiﬁer 10.1109/TII.2012.2209666

Fig. 1 . Basic str ucture of the PLL.

The basic structure of any PLL is shown in Fig

. 1 [7]– [12].

It consists of three blocks: a phase detect

or (PD ), a loop ﬁlter

(LF) and a voltage controlled oscilla

tor (VCO). The input of the

PLL is a continuous-time sinusoidal

signal or the zero crossing

signal

, which is compared w ith

output of the VCO

in the PD. The high-order harmonics

in the phase error

can be ﬁltered out with the LF and th

e output

modiﬁes

the frequency of the VCO. The feed

back action is such that the

phase error is forced to zero. Wh

en zero error is achieved, the

input signal is sampled exac

tlyatzerocrossingsandthePLL

is lo cked. All PLLs have thi

s basic structure and differ mainly

through the various method

s in the impl emen tati on of the PD

[7].

For grid application s, PL L

s are usu ally implemented inside

a higher level control alg

orithm. The y should b e designed with

the goals of having a go

od performa nce and not being exces-

sively resource consu

ming [8]. However, tradeoff alw ays exists

between the performa

nce and the complex ity of the PLLs. In

order to improve the

dynamic resp onse and p recision, different

PDs are proposed to c

onstruct the PLL.

Transformation-ba

sed PDs are common especially in multi-

phase systems, with

the synchronous reference frame (SRF)

[12]–[14], being

the m ost popular. By reducing the band width,

the SRF based PLL

can also operate in grid unbalanced condi-

tions but this is

an inefﬁcient solution [15]. The PDs can also

be designed at t

he ﬁxed reference frame (FRF) [16]. So as to

alleviate the

effect of harmon ic distortion that is present in the

grid voltage,

the adaptive notch ﬁlters (ANFs), also referred to

as second-o

rder generalized integrators (SOGIs), are employed

to reconstr

uct the pu re sinusoidal signal and estimate the funda-

mental fre

quency [6], [16]. In single-phase systems, these trans-

forms are m

ore complex du e to the lack of multiple independent

input var

iables [9]. As such, methods to g enerate secondary or-

thogonal

signals range from transport delay ﬁlters to compl e x

integra

tive feedback networks [17], [18]. Accuracies in these

method

s all rely on the precision of the generated orthogon al

signa

l [7]. To avoid such disadvantage, product-type or mixer

PD sys

tems, which rely on the pr oduct of two sinusoidal signals

to pr

oduce trigonometric relationships between the summation

and d

ifference of the input and estimated signal, are applied to

the

single-phase systems [7].

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