高速AD9854数据手册：300MHz DDS支持多种调制模式

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AD9854是一款高性能的数字模拟转换器（DAC），专为高速数字信号处理应用设计，特别是在通信系统中。这款器件的核心特性包括： 1. 高内部时钟速率：AD9854内置了300 MHz的时钟，这使得它在数据转换速度上表现出色，非常适合需要快速采样和处理的应用。 2. 多种调制模式支持：它支持多种调制技术，如频移键控(FSK)，相移键控(BPSK)，以及正交幅度调制(PSK)，这使得它能够灵活地适应不同的无线通信协议和信号编码。 3. 双通道12位数字-模拟转换器：集成有两个12位的DAC，可以提供高精度的模拟输出，这对于需要精细控制信号波形的系统来说非常重要。 4. 超低噪声性能：配备了超高速比较器，其典型随机噪声（rms）仅为3 ps，这确保了输出信号的高质量和稳定性。 5. 动态性能优越：在100 MHz频率下，具有出色的信道选择性，SFDR（信道选择性比）达到了80 dB，这意味着在宽频带操作中能有效抑制干扰。 6. 可编程功能：AD9854提供了4到20倍可编程参考时钟乘法器，可以方便地调整输出频率；另外，还有双48位频率和14位相位偏移寄存器，允许用户精确地配置输出信号的频率和相位。 7. 信号处理功能：除了基本的调制功能外，还支持线性和非线性频率调制的chirp功能，以及频率阶梯状的频移键控(Frequency-ramped FSK)，这些特性增加了信号的复杂性和灵活性。 8. 单引脚接口：对于FSK和BPSK数据传输，AD9854提供单引脚接口，简化了系统设计，并提高了效率。 9. 小型封装和低功耗：尽管功能强大，但AD9854采用了CMOS工艺，确保了紧凑的封装尺寸和低功耗，适合于空间受限或电源有限的应用。 10. 版权和责任声明：请注意，Analog Devices提供的所有信息虽然被认为是准确可靠的，但不承担因使用该产品可能引起的专利侵权或其他第三方权利侵犯的责任。规格可能会随时更改且不作通知，未经明确许可，不授予任何专利使用权。 AD9854是一款高度集成且功能丰富的高速数字信号处理器，适用于通信、雷达和测试等众多领域，能提供卓越的信号质量和灵活的调制选项。

AD9854

Rev. E | Page 9 of 52

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

80 79 78 77 76 71 70 69 6875 74 73 72

21 22 23 24 25 26 27 28 29 30 31 32 33

NC = NO CONNECT

AD9854

TOP VIEW

(Not to Scale)

WR/SCLK

RD/CS

DVDD

DGND

FSK/BPSK/HOLD

OSK

AVDD

AGND

DVDD

DGND

DVDD

DGND

MASTER RESET

S/P SELECT

REFCLK

DVDD

DGND

AVDD

AGND

DAC R

SET

DACBP

AVDD

AGND

IOUT2

AVDD

IOUT1

PIN 1

INDICATOR

A2/IO RESET

A1/SDO

A0/SDIO

I/O UD CLK

AGND

AVDD

VINN

VINP

AGND

64 63 62 6167 66 65

34 35 36 37 38 39 40

AGND

VOUT

AVDD

AGND

AVDD

DIFF CLK ENABLE

AGND

PLL FILTER

00636-002

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 8 D7 to D0 8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.

9, 10, 23, 24, 25,

73, 74, 79, 80

DVDD

Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND

and DGND.

11, 12, 26, 27, 28,

72, 75 to 78

DGND Connections for the Digital Circuitry Ground Return. Same potential as AGND.

13, 35, 57, 58, 63 NC No Internal Connection.

14 to 16 A5 to A3

Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program

17 A2/IO RESET

Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program

the serial programming mode is selected, allowing an IO RESET of the serial communication bus

that is unresponsive due to improper programming protocol. Resetting the serial bus in this

manner does not affect previous programming, nor does it invoke the default programming

values listed in

Table 8. Active high.

18 A1/SDO

Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program

mode. SDO is used in 3-wire serial communication mode when the serial programming mode is

selected.

19 A0/SDIO

Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program

is used in 2-wire serial communication mode.

AD9854

Rev. E | Page 10 of 52

Pin No. Mnemonic Description

20 I/O UD CLK

Bidirectional I/O Update Clock. Direction is selected in control register. If this pin is selected as an

input, a rising edge transfers the contents of the I/O port buffers to the programming registers. If I/O

UD CLK is selected as an output (default), an output pulse (low to high) with a duration of eight

system clock cycles indicates that an internal frequency update has occurred.

WR/SCLK Write Parallel Data to I/O Port Buffers. Shared function with SCLK. Serial clock signal associated

with the serial programming bus. Data is registered on the rising edge. This pin is shared with

when the parallel mode is selected. The mode is dependent on Pin 70 (S/P SELECT).

RD/CS Read Parallel Data from Programming Registers. Shared function with CS. Chip-select signal

associated with the serial programming bus. Active low. This pin is shared with

RD when the

parallel mode is selected.

29 FSK/BPSK/HOLD

Multifunction pin according to the mode of operation selected in the programming control

selects Phase 1 and logic high selects Phase 2. In chirp mode, logic high engages the hold

function, causing the frequency accumulator to halt at its current location. To resume or

commence chirp mode, logic low is asserted.

30 OSK

Output Shaped Keying. Must first be selected in the programming control register to function. A

logic high causes the I and Q DAC outputs to ramp up from zero-scale to full-scale amplitude at a

preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at the

preprogrammed rate.

31, 32, 37, 38, 44,

50, 54, 60, 65

AVDD

Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND

and DGND.

33, 34, 39, 40, 41,

45, 46, 47, 53, 59,

62, 66, 67

AGND Connections for Analog Circuitry Ground Return. Same potential as DGND.

36 VOUT

Noninverted Output of the Internal High Speed Comparator. Designed to drive 10 dBm to 50 Ω

load as well as standard CMOS logic levels.

42 VINP Voltage Input Positive. The noninverting input of the internal high speed comparator.

43 VINN Voltage Input Negative. The inverting input of the internal high speed comparator.

48 IOUT1 Unipolar Current Output of I, or the Cosine DAC. (Refer to Figure 3.)

IOUT1

Complementary Unipolar Current Output of I, or the Cosine DAC.

IOUT2

Complementary Unipolar Current Output of Q, or the Sine DAC.

52 IOUT2

Unipolar Current Output of Q, or the Sine DAC. This DAC can be programmed to accept external

12-bit data in lieu of internal sine data, allowing the AD9854 to emulate the AD9852 control DAC

function.

55 DACBP

Common Bypass Capacitor Connection for Both I and Q DACs. A 0.01 μF chip capacitor from this

pin to AVDD improves harmonic distortion and SFDR slightly. No connect is permissible, but

results in a slight degradation in SFDR.

56 DAC R

SET

Common Connection for Both I and Q DACs. Used to set the full-scale output current. R

SET

= 39.9/I

OUT

Normal R

SET

range is from 8 kΩ (5 mA) to 2 kΩ (20 mA).

61 PLL FILTER

Connection for the External Zero-Compensation Network of the REFCLK Multiplier’s PLL Loop

Filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF

capacitor. The other side of the network should be connected to AVDD as close as possible to

Pin 60. For optimum phase noise performance, the REFCLK multiplier can be bypassed by setting

the bypass PLL bit in Control Register 1E hex.

64 DIFF CLK ENABLE

Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK

and

REFCLK (Pin 69 and Pin 68, respectively).

REFCLK Complementary (180° Out of Phase) Differential Clock Signal. User should tie this pin high or low

when single-ended clock mode is selected. Same signal levels as REFCLK.

69 REFCLK

Single-Ended Reference Clock Input (CMOS Logic Levels Required) or One of Two Differential

Clock Signals. In differential reference clock mode, both inputs can be CMOS logic levels or have

greater than 400 mV p-p square or sine waves centered about 1.6 V dc.

70 S/P SELECT Selects serial programming mode (logic low) or parallel programming mode (logic high).

71 MASTER RESET

Initializes the serial/parallel programming bus to prepare for user programming; sets

programming registers to a do-nothing state defined by the default values listed in

Table 8.

Active on logic high. Asserting this pin is essential for proper operation upon power-up.

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