"TI-DS92LV2421.pdf：LVDS串行器技术规格"

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TI-DS92LV2421.pdf is a document providing detailed information about the DS92LV2421, a Low Voltage Differential Signaling (LVDS) serializer from Texas Instruments. The DS92LV2421 is designed to be used for graphics processing, specifically for connecting a graphic processor to a display using the Channel Link II interface. The document specifies the pinouts, voltage requirements, and optional configurations for the serializer. It also outlines the recommended circuitry for connecting the DS92LV2421 to an ASIC/FPGA or a 24-bit RGB display. The DS92LV2421 operates with a 100 ohm shielded twisted pair (STP) cable and requires a power supply voltage, VDDIO, and a power-down mode, PDB. The configuration also includes pins for various functions such as clock input, data input and output, and control signals. Additionally, the document provides information on optional features such as de-emphasis, built-in self-test (BIST), and the use of strap pins for configuration. The serializer uses LVDS technology to transmit high-speed digital video and imaging data between devices while reducing electromagnetic interference. LVDS is a popular interface for connecting components in electronic systems due to its high data rate and low power consumption. In summary, the TI-DS92LV2421.pdf document is a comprehensive guide for integrating and configuring the DS92LV2421 LVDS serializer in graphics processing applications. It provides engineers and designers with the necessary information to successfully implement the serializer in their systems and optimize the performance of the connected components.

DS92LV2421

DS92LV2422

www.ti.com

SNLS321C –MAY 2010–REVISED MAY 2016

Product Folder Links: DS92LV2421 DS92LV2422

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Based on nine thermal vias.

6.4 Thermal Information

Over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC

(1)

DS92LV2421 DS92LV2422

UNITRHS (WQFN) NKB (WQFN)

48 PINS 60 PINS

θJA

Junction-to-ambient thermal resistance

(2)

30.3 26.9 °C/W

θJC(top)

Junction-to-case (top) thermal resistance

(2)

11.5 9.1 °C/W

θJB

Junction-to-board thermal resistance 7.3 6 °C/W

Junction-to-top characterization parameter 0.1 0.1 °C/W

Junction-to-board characterization parameter 7.3 6 °C/W

θJC(bot)

Junction-to-case (bottom) thermal resistance 2.7 1.5 °C/W

(1) The electrical characteristics tables list verified specifications under the listed recommended operating conditions except as otherwise

modified or specified by the electrical characteristics conditions or notes. Typical specifications are estimations only and are not verified.

(2) Typical values represent most likely parametric norms at V

= 3.3 V, T

= 25°C, and at the recommended operation conditions at the

time of product characterization and are not verified.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V

, ΔV

, V

, and V

, which are differential voltages.

6.5 Electrical Characteristics – Serializer DC

Over recommended operating supply and temperature ranges (unless otherwise noted).

(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVCMOS INPUT DC SPECIFICATIONS

High level input voltage

DDIO

= 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB,

VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)

2.2 V

DDIO

= 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB,

VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)

0.65 × V

DDIO

Low level input voltage

DDIO

= 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB,

VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)

GND 0.8

DDIO

= 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB,

VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)

GND 0.35 × V

DDIO

Input current

= 0 V or V

DDIO

(DI[23:0],

CI1,CI2,CI3, CLKIN, PDB, VODSEL,

RFB, BISTEN, and CONFIG[1:0] pins)

DDIO

= 3 V to 3.6 V –15 ±1 15

μA

DDIO

= 1.7 V to 1.89 V –15 ±1 15

CML DRIVER DC SPECIFICATIONS

Differential output voltage

= 100 Ω, de-emphasis = disabled

(see Figure 2; DOUT+ and DOUT–

pins)

VODSEL = 0 ±205 ±280 ±355

VODSEL = 1 ±320 ±420 ±520

VOD

p-p

Differential output voltage

(DOUT+) – (DOUT-)

= 100 Ω, de-emphasis = disabled

(see Figure 2; DOUT+ and DOUT–

pins)

VODSEL = 0 560

p-p

VODSEL = 1 840

ΔV

Output voltage unbalance

= 100 Ω, de-emphasis = disabled, VODSEL = L (DOUT+ and

DOUT– pins)

1 50 mV

Offset voltage

(single-ended)

At TP A and B (see Figure 1), R

100 Ω, de-emphasis = disabled

(DOUT+ and DOUT– pins)

VODSEL = 0 1.65

VODSEL = 1 1.575

ΔV

Offset voltage unbalance

(single-ended)

At TP A and B (see Figure 1), R

= 100 Ω,

de-emphasis = disabled (DOUT+ and DOUT– pins)

1 mV

Output short circuit current

DOUT± = 0 V, de-emphasis = disabled,

VODSEL = 0 (DOUT+ and DOUT– pins)

–36 mA

Internal output termination

resistor

DOUT+ and DOUT– pins 80 100 120 Ω

DS92LV2421

DS92LV2422

SNLS321C –MAY 2010–REVISED MAY 2016

www.ti.com

Product Folder Links: DS92LV2421 DS92LV2422

Electrical Characteristics – Serializer DC (continued)

Over recommended operating supply and temperature ranges (unless otherwise noted).

(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

DDT1

Serializer supply current

(includes load current)

= 100 Ω, CLKIN = 75 MHz,

checker board pattern,

de-emphasis = 3 kΩ, VODSEL = H

(see Figure 9)

= 1.89 V 75 90

mAV

DDIO

= 1.89 V 3 5

DDIOT1

DDIO

= 3.6 V 11 15

DDT2

Serializer supply current

(includes load current)

= 100 Ω, CLKIN = 75 MHz,

checker board pattern,

de-emphasis = 6 kΩ, VODSEL = L

(see Figure 9)

= 1.89 V 65 80

mAV

DDIO

= 1.89 V 3 5

DDIOT2

DDIO

= 3.6 V 11 15

DDZ

Serializer supply current

power-down

PDB = 0 V, All other LVCMOS Inputs

= 0 V

= 1.89 V 40 1000

µAV

DDIO

= 1.89 V 5 10

DDIOZ

DDIO

= 3.6 V 10 20

(1) Specification is verified by characterization and is not tested in production.

6.6 Electrical Characteristics – Deserializer DC

Over recommended operating supply and temperature ranges (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

3.3-V I/O LVCMOS DC SPECIFICATIONS (V

DDIO

= 3 V TO 3.6 V)

High level input voltage PDB and BISTEN pins 2.2 V

DDIO

Low level input voltage PDB and BISTEN pins GND 0.8 V

Input current V

= 0 V or V

DDIO

(PDB and BISTEN pins) −15 ±1 15 μA

High level output voltage

= −2 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1,

CO2, CO3, CLKOUT, LOCK, and PASS pins)

2.4 V

DDIO

Low level output voltage

= 3 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1,

CO2, CO3, CLKOUT, LOCK, and PASS pins)

GND 0.4 V

Output short circuit current

DDIO

= 3.3 V, V

OUT

= 0 V, OS_CLKOUT/DATA = L/H

(CLKOUT pin)

Output short circuit current

DDIO

= 3.3 V, V

OUT

= 0 V, OS_CLKOUT/DATA = L/H

(output pins)

TRI-STATE output current PDB = 0 V, OSS_SEL = 0 V, V

OUT

= H (output pins) −15 15 µA

1.8-V I/O LVCMOS DC SPECIFICATIONS (V

DDIO

= 1.71 V to 1.89 V)

High level input voltage PDB and BISTEN pins 1.235 V

DDIO

Low level input voltage PDB and BISTEN pins GND 0.595 V

Input current V

= 0 V or V

DDIO

(PDB and BISTEN pins) −15 ±1 15 μA

High level output voltage

= –2 mA, OS_CLKOUT/DATA = L/H (DO[23:0],

CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins)

DDIO

– 0.45 V

DDIO

Low level output voltage

= 2 mA, OS_CLKOUT/DATA = L/H (DO[23:0],

CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins)

GND 0.45 V

Output short circuit current

DDIO

= 1.8 V, V

OUT

= 0 V, OS_CLKOUT/DATA = L/H

(CLKOUT pin)

Output short circuit current

DDIO

= 1.8 V, V

OUT

= 0 V, OS_CLKOUT/DATA = L/H

(output pins)

TRI-STATE output current

PDB = 0 V, OSS_SEL = 0 V, V

OUT

= 0 V or V

DDIO

(output pins)

–15 15 µA

CML RECEIVER DC SPECIFICATIONS

Differential input threshold high

voltage

= 1.2 V, RIN+ and RIN- pins (Internal V

BIAS

) 50 mV

Differential input threshold low voltage V

= 1.2 V, RIN+ and RIN- pins (Internal V

BIAS

) –50 mV

Common mode voltage RIN+ and RIN- pins (Internal V

BIAS

) 1.2 V

Input current V

= 0 V or V

DDIO

, RIN+ and RIN- pins –15 15 µA

Internal input termination resistor RIN+ and RIN- pins 80 100 120 Ω

LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS (EQ TEST PORT

(1)

)

Differential output voltage ROUT+ and ROUT- pins, R

= 100 Ω 542 mV

Offset voltage

(single-ended)

ROUT+ and ROUT- pins, R

= 100 Ω 1.4 V

DS92LV2421

DS92LV2422

www.ti.com

SNLS321C –MAY 2010–REVISED MAY 2016

Product Folder Links: DS92LV2421 DS92LV2422

Electrical Characteristics – Deserializer DC (continued)

Over recommended operating supply and temperature ranges (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Internal termination resistor ROUT+ and ROUT- pins 80 100 120 Ω

SUPPLY CURRENT

DD1

Deserializer supply current (includes

load current)

CLKOUT = 75 MHz, checker

board pattern,

OS_CLKOUT/DATA = H,

= 4 pF (see Figure 9)

= 1.89 V 97 115

DDIO1

DDIO

= 1.89 V 40 50

DDIO

= 3.6 V 75 85

DDZ

Deserializer supply current power

down

PDB = 0 V, All other LVCMOS

Inputs = 0 V

= 1.89 V 100 3000

µAV

DDIO

= 1.89 V 6 50

DDIOZ

DDIO

= 3.6 V 12 100

(1) Specification is verified by characterization and is not tested in production.

6.7 Electrical Characteristics – DC and AC Serial Control Bus

Over 3.3-V supply and temperature ranges (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input high level SDA and SCL 2.2 V

DDIO

Input low level voltage SDA and SCL GND 0.8 V

Input hysteresis >50 mV

Output low level voltage

(1)

SDA, I

= 1.25 mA, V

DDIO

= 3.3 V 0 0.4 V

Input current SDA or SCL, Vin = V

DDIO

or GND –15 15 µA

Input capacitance SDA or SCL <5 pF

6.8 Timing Requirements – DC and AC Serial Control Bus

Over 3.3-V supply and temperature ranges (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SDA rise time (read) SDA, RPU = 10 kΩ, Cb ≤ 400 pF 40 ns

SDA fall time (read) SDA, RPU = 10 kΩ, Cb ≤ 400 pF 25 ns

SU;DAT

Set up time (read) 520 ns

HD;DAT

Hold up time (read) 55 ns

Input filter 50 ns

6.9 Timing Requirements – Serializer for CLKIN

Over recommended operating supply and temperature ranges (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

TCP

Transmit input CLKIN period 10 MHz to 75 MHz (see Figure 4) 13.3 T 100 ns

TCIH

Transmit input CLKIN high time 10 MHz to 75 MHz (see Figure 4) 0.4 × T 0.5 × T 0.6 × T ns

TCIL

Transmit input CLKIN low time 10 MHz to 75 MHz (see Figure 4) 0.4 × T 0.5 × T 0.6 × T ns

CLKT

CLKIN input transition time 10 MHz to 75 MHz (see Figure 4) 0.5 2.4 ns

SSC

CLKIN input

fmod (spread spectrum at 75 MHz) 35 kHz

fdev (spread spectrum at 75 MHz) ±2%

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