RENO: A High-efficient Reconfigurable Neuromorphic
Computing Accelerator Design
∗
Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Hai Li, Yiran Chen
University of Pittsburgh
Pittsburgh, USA
{xil116, mem231, bel34, hal66, yic52}@pitt.edu
Boxun Li, Yu Wang
Tsinghua University
Beijing, P.R. China
{lbx13, yu-wang}@mails.tsinghua.edu.cn
Hao Jiang
San Francisco State University
San Francisco, USA
jianghao@sfsu.edu
Mark Barnell, Qing Wu
Air Force Research Laboratory
Rome, USA
{mark.barnell.1, qing.wu.2}@us.af.mil
Jianhua Yang
University of Massachusetts
Amherst, USA
jjyang@umass.edu
ABSTRACT
Neuromorphic computing is recently gaining significant at-
tention as a promising candidate to conquer the well-known
von Neumann bottleneck. In this work, we propose RENO
– a efficient reconfigurable neuromorphic computing acceler-
ator. RENO leverages the extremely efficient mixed-signal
computation capability of memristor-based crossbar (MBC)
arrays to speedup the executions of artificial neural networks
(ANNs). The hierarchically arranged MBC arrays can be
configured to a variety of ANN topologies through a mixed-
signal interconnection network (M-Net). Simulation results
on seven ANN applications show that compared to the base-
line general-purpose processor, RENO can achieve on av-
erage 178.4× (27.06×) performance speedup and 184.2×
(25.23×) energy savings in high-efficient multilayer percep-
tion (high-accurate auto-associative memory) implementa-
tion. Moreover, in the comparison to a pure digital neural
processing unit (D-NPU) and a design with MBC arrays co-
operating through a digital interconnection network, RENO
still achieves the fastest execution time and the lowest en-
ergy consumption with similar computation accuracy.
1. INTRODUCTION
Traditional von Neumann computers require frequent data
exchanging between processors and memory chips. This de-
sign severely limits the system performance and efficiency,
especially in computation-intensive cognitive applications.
As a promising candidate to overcome the inefficiency of
von Neumann architecture, neuromorphic systems recently
became a hot research area in future tera-scale computing.
Many studies have been conducted on the hardware imple-
mentation of artificial neural networks (ANNs) across both
digital and analog domains. Examples include neural net-
∗
This work is supported in part by NSF XPS-1337198, NSF CNS-
1116171, AFRL FA8750-15-2-0048, DARPA D13AP00042, HP Lab
Innov. Res. Pgm, NSFC 61373026, and Tsinghua Univ. Init. Sci.
Res. Pgm. Received and approved for public release by AFRL on
03/04/2015, case number 88ABW-2015-0833. Any Opinions, findings,
and conclusions or recommendations expressed in this material are
those of the authors and do not necessarily reflect the views of AFRL
or its contractors.
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work accelerators for signal processing [5], digital approxi-
mate computing accelerators that leverage neural network
algorithms [8], and heterogeneous systems built with GPUs
and APUs for deep learning accelerations [9]. However, tra-
ditional CMOS technology has been proven to be inefficient
for neuromorphic system design as dozens of transistors are
usually required to build one neuron [5].
Discovery of nanoscale memristor devices [6] inspired an
exciting approach to implement neuromorphic systems. Par-
ticularly, the similarity between the programmable resis-
tance state of memristors and the variable synaptic strengths
of biological synapses dramatically simplify the circuit real-
ization of neural network models. The specialty of memris-
tors has been investigated and exploited in a few research
works that focus on either the circuit implementation of the
matrix-vector multiplications in conventional approximate
computing acceleration [16, 17].
In this work, we propose RENO – a novel efficient re-
configurable neuromorphic computing accelerator. RENO
uses on-chip memristor-based crossbar (MBC) arrays to im-
plement a perceptron networks, aiming at the acceleration
of ANN computations. Unlike many neuromorphic systems
that perform the computations on pure digital ALUs or ana-
log approximate computing units with AD/DA interface,
our design adopts a hybrid method in data representation:
the computation within the MBC arrays and the signal com-
munications among the MBC arrays are conducted in analog
form, while the control information remains as digital sig-
nals. Compared to the existing implementations of digital
ANN accelerators and approximate computing units, the key
distinctions of RENO can be summarized as:
• A efficient memristor-based mixed-signal accel-
erator is designed to speed up neuromorphic comput-
ing and support the implementations of a variety of
neural network topologies;
• A mixed-signal interconnection network (M-Net)
is proposed to assist the communication of computa-
tional signals among the MBCs.
• An optimized configuration is discussed and final-
ized by thoroughly analyzing the impact of various de-
sign parameters on the system performance/accuracy.
RENO offers a cost-efficient and fault-tolerant ANN com-
putation platform complementing the general computations
of CPU cores. In the evaluations of RENO, we adopt a set
of prevailing ANN benchmarks and two ANN topologies-
Multilayer perception (MLP) and auto-associative memory
(AAM) to demonstrate the tradeoffs of the computation
performance and accuracy for different RENO configura-
tions. Simulation results show that compared to the baseline