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首页三星S3C2416X ARM9处理器用户手册
"ARM9 S3C2416X 手册 原版,三星2416 ARM9 使用手册"
本文档详细介绍了三星S3C2416X,一款基于ARM9架构的16/32位RISC(精简指令集计算)微处理器。该处理器是专为嵌入式应用设计的,常见于移动设备、工业控制以及消费类电子产品中。手册的发布日期为2009年1月,版本号为REV1.20,由三星电子公司发布并享有版权。
**ARM9 S3C2416X关键特性**
1. **处理器核心**: ARM920T内核,支持Thumb指令集,提供高性能与低功耗的平衡。
2. **内存接口**: 内置高速存储器接口,如SDRAM和ROM,支持快速数据访问。
3. **外围接口**: 集成了多种外围接口,如UART、I2C、SPI、USB主机/设备端口、以太网MAC、LCD控制器等,方便系统集成。
4. **电源管理**: 强大的电源管理功能,支持动态电压和频率调整(DVFS),以优化能效。
5. **安全特性**: 可能包含硬件加密引擎,用于数据保护和安全通信。
**重要注意事项**
- 三星对出版物中的信息进行了仔细校验,但不保证在发布时完全准确。对于可能存在的错误或遗漏,三星不承担责任。
- 三星保留随时更改产品或产品规格的权利,以提升功能或设计,而无需提前通知,并且无义务更新此文档以反映这些变化。
- 购买半导体设备的用户并未因购买而获得三星或任何其他方的专利权许可。
- 三星不对其产品的适用性、特定用途的性能做任何保证,也不承担因产品应用或使用导致的任何责任。
**系统设计与开发**
- 开发者需要根据手册提供的技术规格来设计电路板和软件。
- 在设计过程中,应遵循三星提供的电气规范、布局指导和热管理建议,以确保系统的稳定运行。
- 用户需自行负责获取必要的软件开发工具,例如IDE、编译器、调试器等,以编写和调试针对S3C2416X的应用程序。
- 对于实时操作系统(RTOS)和嵌入式Linux等操作系统的选择和移植,开发者需要参考手册中的系统初始化流程和中断处理机制。
**编程与调试**
- S3C2416X支持JTAG接口进行硬件调试,开发者可以使用专用的ARM调试工具链进行代码调试。
- 手册将详细说明寄存器配置、中断服务例程(ISRs)的设置以及外设驱动的编写方法。
**安全与可靠性**
- 为了保证系统安全,开发者需要了解并正确配置处理器的安全特性,如防止非法访问的内存保护单元(MPU)和看门狗定时器。
- 硬件故障和异常处理机制也需要在设计阶段考虑,以提高系统的可靠性。
**总结**
S3C2416X是一款高度集成的嵌入式处理器,适用于各种需要高性能和低功耗的场合。开发人员需要结合手册提供的详细信息,进行系统设计、软件开发和硬件调试工作,确保产品能够满足预期的功能和性能需求。同时,注意三星的免责声明,理解其对产品变更的政策,以及对知识产权的保护。
xii S3C2416X RISC MICROPROCESSOR
Table of Contents (Continued)
Chapter 20 SD/MMC Host Controller (Continued)
5.13 Block Gap Control Register ...........................................................................................................20-38
5.14 Wakeup Control Register...............................................................................................................20-40
5.15 Clock Control Register...................................................................................................................20-41
5.16 Timeout Control Register...............................................................................................................20-43
5.17 Software Reset Register................................................................................................................20-44
5.18 Normal Interrupt Status Register ...................................................................................................20-46
5.19 Error Interrupt Status Register.......................................................................................................20-50
5.20 Normal Interrupt Status Enable Register.......................................................................................20-53
5.21 Error Interrupt Status Enable Register ..........................................................................................20-55
5.22 Normal Interrupt Signal Enable Register.......................................................................................20-56
5.23 Error Interrupt Signal Enable Register...........................................................................................20-58
5.24 Autocmd12 Error Status Register..................................................................................................20-59
5.25 Capabilities Register......................................................................................................................20-61
5.26 Maximum Current Capabilities Register........................................................................................20-63
5.27 Control Register 2..........................................................................................................................20-64
5.28 Control Register 3..........................................................................................................................20-67
5.29 Debug Register..............................................................................................................................20-68
5.30 Control Register 4..........................................................................................................................20-68
5.31 Force Event Register for Auto CMD12 Error Status......................................................................20-69
5.32 Force Event Register for Error Interrupt Status.............................................................................20-70
5.33 ADMA Error Status Register..........................................................................................................20-71
5.34 ADMA System Address Register...................................................................................................20-73
5.35 HOST Controller Version Register ................................................................................................20-74
Chapter 21 LCD Controller
1 Overview....................................................................................................................................................21-1
1.1 Features...........................................................................................................................................21-2
2 Functional Description...............................................................................................................................21-3
2.1 Brief of the sub-block .......................................................................................................................21-3
2.2 Data Flow.........................................................................................................................................21-3
2.3 Interface ...........................................................................................................................................21-4
2.4 Overview of the Color Data..............................................................................................................21-5
2.5 VD signal Connection ......................................................................................................................21-18
2.6 Palette usage...................................................................................................................................21-20
3 Window Blending.......................................................................................................................................21-22
3.1 Overview ..........................................................................................................................................21-22
3.2 Blending Diagram/Details ................................................................................................................21-23
4 Vtime Controller Operation........................................................................................................................21-26
4.1 RGB Interface ..................................................................................................................................21-26
4.2 I80-System Interface........................................................................................................................21-26
5 Virtual Display ...........................................................................................................................................21-27
6 RGB Interface I/O......................................................................................................................................21-28
7 LCD CPU Interface I/O (I80-system I/F) ...................................................................................................21-29
8 Programmer’s Model.................................................................................................................................21-31
8.1 Overview ..........................................................................................................................................21-31
S3C2416X RISC MICROPROCESSOR xiii
Table of Contents (Continued)
Chapter 22 ADC & Touch Screen Interface
1 Overview ...................................................................................................................................................22-1
1.1 Features...........................................................................................................................................22-1
2 ADC & Touch Screen Interface Operation................................................................................................22-2
2.1 Block Diagram .................................................................................................................................22-2
2.2 Function Descriptions......................................................................................................................22-3
3 ADC and Touch Screen Interface Special Registers................................................................................22-5
3.1 ADC Control (ADCCON) Register...................................................................................................22-5
3.2 ADC Touch Screen Control (ADCTSC) Register............................................................................22-6
3.3 ADC Start Delay (ADCDLY) Register..............................................................................................22-7
3.4 ADC Conversion Data (ADCDAT0) Register ..................................................................................22-8
3.5 ADC Conversion Data (ADCDAT1) Register ..................................................................................22-9
3.6 ADC Touch Screen up-Down Int Check Register (ADCUPDN)......................................................22-9
3.7 ADC Channel Mux Register (ADCMUX) .........................................................................................22-10
Chapter 23 IIS Multi Audio Interface
1 Overview ...................................................................................................................................................23-1
2 Feature......................................................................................................................................................23-1
3 Signals ......................................................................................................................................................23-1
4 Block Diagram...........................................................................................................................................23-2
5 Functional Descriptions.............................................................................................................................23-2
5.1 Master/Slave Mode..........................................................................................................................23-3
5.2 DMA Transfer ..................................................................................................................................23-4
6 Audio Serial Data Format..........................................................................................................................23-5
6.1 IIS-Bus Format ................................................................................................................................23-5
6.2 MSB (Left) Justified .........................................................................................................................23-5
6.3 LSB (Right) Justified........................................................................................................................23-5
6.4 Sampling Frequency and Master Clock ..........................................................................................23-7
6.5 IIS Clock Mapping Table .................................................................................................................23-7
7 Programming Guide..................................................................................................................................23-8
7.1 Initialization......................................................................................................................................23-8
7.2 Play Mode (TX mode) with DMA .....................................................................................................23-8
7.3 Recording Mode (RX mode) with DMA ...........................................................................................23-8
7.4 Example Code .................................................................................................................................23-9
8 IIS-BUS Interface Special Registers.........................................................................................................23-15
8.1 IIS Control Register (IISCON) .........................................................................................................23-16
8.2 IIS Mode Register (IISMOD) ...........................................................................................................23-18
8.3 IIS FIFO Control Register (IISFIC) ..................................................................................................23-20
8.4 IIS Pres
caler Control Register (IISPSR)..........................................................................................23-20
8.5 IIS Transmit Register (IISTXD)........................................................................................................23-21
8.6 IIS Receive Register (IISRXD) ....................................................................................................... 23-21
xiv S3C2416X RISC MICROPROCESSOR
Table of Contents (Continued)
Chapter 24 AC97 Controller
1 Overview....................................................................................................................................................24-1
1.1 Feature.............................................................................................................................................24-1
1.2 Signals .............................................................................................................................................24-1
2 AC97 Controller Operation........................................................................................................................24-2
2.1 Block Diagram..................................................................................................................................24-2
2.2 Internal Data Path............................................................................................................................24-3
3 Operation Flow Chart ................................................................................................................................24-4
4 AC-link Digital Interface Protocol ..............................................................................................................24-5
4.1 AC-link Output Frame (SDATA_OUT).............................................................................................24-6
4.2 AC-link Input Frame (SDATA_IN)....................................................................................................24-7
5 AC97 Power-Down....................................................................................................................................24-9
6 Codec Reset..............................................................................................................................................24-10
7 AC97 Controller State Diagram.................................................................................................................24-11
8 AC97 Controller Special Registers............................................................................................................24-12
8.1 AC97 Special Funcion Register Summary ......................................................................................24-12
8.2 AC97 Global Control Register (AC_GLBCTRL) ..............................................................................24-13
8.3 AC97 Global Status Register (AC_GLBSTAT)................................................................................24-14
8.4 AC97 Codec Command Register (AC_CODEC_CMD) ..................................................................24-14
8.5 AC97 Codec Status Register (AC_CODEC_STAT)........................................................................24-15
8.6 AC97 PCM Out/In Channel Fifo Address Register (AC_PCMADDR).............................................24-15
8.7 AC97 MIC In Channel FIFO Address Register (AC_MICADDR) ....................................................24-16
8.8 AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA)
.................................................24-16
8.9 AC97 MIC In Channel FIFO Data Register (AC_MICDATA)...........................................................24-16
S3C2416X RISC MICROPROCESSOR xv
Table of Contents (Continued)
Chapter 25 PCM Audio Interface
1 Overview ...................................................................................................................................................25-1
1.1 Feature ............................................................................................................................................25-1
1.2 Signals.............................................................................................................................................25-1
2 PCM Audio Interface.................................................................................................................................25-2
3 PCM Timing ..............................................................................................................................................25-3
3.1 PCM Input Clock Diagram...............................................................................................................25-4
3.2 PCM Registers ................................................................................................................................25-5
3.3 PCM Register Summary..................................................................................................................25-5
3.4 PCM Control Register......................................................................................................................25-6
3.5 PCM CLK Control Register .............................................................................................................25-8
3.6 The PCM Tx FIFO Register.............................................................................................................25-9
3.7 PCM Rx FIFO Register....................................................................................................................25-10
3.8 PCM Interrupt Control Register .......................................................................................................25-11
3.9 PCM Interrupt Status Register ........................................................................................................25-14
3.10 PCM FIFO Status Register............................................................................................................25-16
3.11 PCM Interrupt Clear Register ........................................................................................................25-17
Chapter 26 Electrical Data
1 Absolute Maximum Ratings ......................................................................................................................26-1
2 Recommended Operating Conditions.......................................................................................................26-2
3 D.C. Electrical Characteristics ..................................................................................................................26-4
4 A.C. Electrical Characteristics ..................................................................................................................26-6
Chapter 27 Mechanical Data
1 Package Dimensions ................................................................................................................................27-1
xvi S3C2416X RISC MICROPROCESSOR
List of Figures
Figure Title Page
Number Number
1-1 S3C2416 Block Diagram..............................................................................................1-5
1-2 S3C2416 Pin Assignments (400-FBGA) Top view ......................................................1-6
1-3 Memory Map ................................................................................................................1-32
2-1 System Controller Block Diagram................................................................................2-2
2-2 Power-On Reset Sequence .........................................................................................2-4
2-3 Clock Generator Block Diagram ..................................................................................2-6
2-4 Main Oscillator Circuit Examples .................................................................................2-7
2-5 PLL(Phase-Locked Loop) Block Diagram....................................................................2-8
2-6 The Case that Changes Slow Clock by Setting PMS Value........................................2-8
2-7 The Clock Distribution Block Diagram .........................................................................2-9
2-8 MPLL Based Clock Domain .........................................................................................2-9
2-9 EPLL Based Clock Domain..........................................................................................2-12
2-10 Power Mode State Diagram.........................................................................................2-13
2-11 Entering STOP Mode and Exiting STOP Mode (wake-up)..........................................2-17
2-12 Entering SLEEP Mode and Exiting SLEEP Mode (wake-up) ......................................2-18
2-13 Usage of PWROFF_SLP .............................................................................................2-34
3-1 The Configuration of MATRIX and Memory Sub-System of S3C2416........................3-1
5-1 SMC Block Diagram.....................................................................................................5-3
5-2 SMC Core Block Diagram............................................................................................5-3
5-3 External Memory Two Output Enable Delay State Read.............................................5-4
5-4 Read Timing Diagram (DRnCS = 1, DRnOWE = 0) ....................................................5-4
5-5 Read Timing Diagram (DRnCS = 1, DRnOWE = 1) ....................................................5-5
5-6
External Burst ROM with WSTRD=2 and WSTBRD=1 Fixed Length Burst Read ......5-6
5-7 External Synchronous Fixed Length Four Transfer Burst Read..................................5-7
5-8 External Memory Two Write Enable Delay State Write ...............................................5-8
5-9 Write Timing Diagram (DRnCS = 1, DRnOWE = 0) ....................................................5-9
5-10 Write Timing Diagram (DRnCS = 1, DRnOWE = 1) ....................................................5-9
5-11 Synchronous Two Wait State Write .............................................................................5-10
5-12 Read, then two Writes (WSTRD=WSTWR=0), Two Turnaround Cycles (IDCY=2)....5-11
5-13 Memory Interface with 8-bit SRAM (2MB) ...................................................................5-13
5-14 Memory Interface with 16-bit SRAM (4MB) .................................................................5-13
6-1 Mobile DRAM Controller Block Diagram......................................................................6-2
6-2 Memory Interface with 16-bit SDRAM (4Mx16, 4banks) .............................................6-4
6-3 Memory Interface with 32-bit SDRAM (4Mx16 * 2ea, 4banks) ....................................6-4
6-4 Memory Interface with 16-bit Mobile DDR and DDR2 .................................................6-5
6-5 DRAM Timing Diagram ................................................................................................6-6
6-6 CL (CAS Latency) Timing Diagram..............................................................................6-6
6-7 t
ARFC
Timing Diagram..................................................................................................6-7
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