自动内存分区与调度：提升嵌入式系统性能与功耗

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"这是一份关于计算机组成原理的英文版课件，名为'10-ACMTODAESBestPaperAward.pdf'。该文档聚焦于自动内存分区与调度在提升现代嵌入式系统性能和能耗优化中的关键作用。随着计算机性能需求的爆炸性增长，内存瓶颈已成为设计中的一个重要限制因素。为了加速特定计算任务，如通过循环（nest loops）实现的算法，已经采用了先进的优化技术，如循环块化（loop tiling）和循环流水线化。论文的主要研究集中在如何解决内存带宽瓶颈问题，这阻碍了设计在可用并行度方面的最佳性能。作者Jason Cong、Wei Jiang、Bin Liu和Yizou提出了一种自动内存分区技术，旨在在给定的吞吐量约束和平台要求下，有效提高流水线循环内核的执行效率，并降低能耗。他们的方法特别关注硬件同步设计中对内存带宽需求的精确满足，首先通过考虑周期准确的调度信息来确保这些硬性要求。该方案分为两步：第一步是基于周期级的调度，确保内存带宽使用满足严格的硬件设计规范；第二步则处理更一般化的数组访问，超越精细的数组引用模式。这种方法的优势在于其灵活性，能够适应各种复杂的内存访问模式，从而在保持性能的同时，减少不必要的能源消耗。这对于当今高度依赖性能和能效的嵌入式系统设计来说，是一项重要的创新贡献。通过这份论文，研究人员探讨了如何在硬件层面进行深度优化，以应对不断增长的计算需求和能源效率挑战。"

Automatic Memory Partitioning and Scheduling for Throughput and Power Optimization 15:5

Fig. 2. A loop pipelining example.

We can easily construct the polytope which contains the iteration space from loop

structures. For the example above, the iteration space is integer points inside polytope:

={i, j∈Q

|0 ≤ i ≤ N, i ≤ j ≤ M}.

The corresponding values of A, B, p and c in Deﬁnition 4 can also be calculated from

the given form:

⎧

⎪

⎨

⎪

⎩

I ∈ Q

⎡

⎢

⎣

−10

−11

0 −1

⎤

⎥

⎦

∗





≥

⎡

⎢

⎣

−N

−M

⎤

⎥

⎦

⎫

⎪

⎬

⎪

⎭

If array access R

is an afﬁne array access R

(I) = M ∗ I + V , the number of accesses

on this element is the number of integer point inside the intersection of iteration space

I and the hyperplane {I|A = M ∗ I + V }. For instance, the number of loop iterations

that access array location A[a1, a2] is a polytope

{i, j|i − 1 = a

, i + j = a

, 0 ≤ i ≤ N, i ≤ j ≤ M}.

The polytope model provides a useful abstract of the array access behavior, which

can be used to ﬁnd the array access frequency for power optimization. Details will be

discussed later.

2.2. Loop Pipelining

Loop pipelining is the most commonly used technique for improving throughput; it al-

lows simultaneous execution of operations in several continuous loop iterations. Modulo

scheduling [Rau 1994] is a loop pipelining technique which tries to ﬁnd a schedule for

one iteration of the loop such that when this same schedule is repeated at regular inter-

vals, no intra- or inter-iteration dependence is violated, and no resource usage conﬂict

arises between operations of either the same or different iterations. This constant in-

terval between the start of successive iterations is termed the initiation interval (II),

usually measured in clock cycles in s ynchronized hardware designs. An example is

shown in Figure 2, which has II = 1.

Deﬁnition 5. The minimum initiation interval MII is a lower bound on the smallest

possible value of II for which a modulo schedule exists.

The lower bound MII is limited by two factors: resource limits and inter-iteration loop

dependence, which are termed as resource-constrained MII (ResM I I) and recurrence-

constrained MII(Rec M I I) respectively. Thus, MII ≥ MAX(ResM I I, RecM I I).

In a pipelined design, each operation in a loop body is executed once within II cycles,

so obviously ResI I ∗ resour ces  operations,orResI I ≥ operations/resour ces.For

memory access, if the memory port number is N, and there are K memory accesses,

ACM Transactions on Design Automation of Electronic Systems, Vol. 16, No. 2, Article 15, Pub. date: March 2011.

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自动内存分区与调度：提升嵌入式系统性能与功耗

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