武汉新芯XM25QH128AHIG NOR闪存规格书：单电源操作与低功耗特性

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武汉新芯(XMC)生产的XM25QH128AHIG是一款高性能的NOR闪存芯片，其规格书在初步修订Rev.H版本中发布，日期为2018年8月6日。该闪存具有以下关键特性： 1. **单电源操作**：支持宽电压范围，工作在2.7到3.6伏之间，兼容性强，适应多种应用环境。 2. **串行接口架构**： - 支持SPI兼容模式，包括模式0和模式3，灵活性高。 - 提供标准、双SPI或四SPI接口选项，分别对应不同的引脚配置（如CLK, CS#, DI, DO, WP#, HOLD#, RESET#等）。 - 可配置的伪随机数据（dummy cycle）数量，有助于提高通信效率。 3. **存储容量**：128M比特（16MB或16384KB）的闪存，共65535个页面，每个可编程页大小为256字节。 4. **高速性能**： - 高速读取：正常模式下，可达50MHz；快速读取（单数据速率模式）下，标准SPI支持104MHz速度，最多伴随1个伪随机数据； - 双SPI和四SPI接口提供相同的速度，但伴随的伪随机数据不同。 5. **功能特性**： - 写入挂起（Write Suspend）和恢复（Write Resume）功能，便于在执行其他任务时暂停或恢复写入操作。 - 支持Serial Flash Discoverable Parameters (SFDP)签名，方便设备自动识别和配置。 6. **低功耗设计**： - 活动状态下典型电流仅为5mA，大大降低能耗。 - 在待机模式下，典型功耗低至1μA，延长电池寿命。 7. **统一的扇区结构**： - 4096个4KB扇区，便于管理和数据保护。 - 512个32KB块和256个64KB块，提供了灵活的存储分区选项。 XM25QH128AHIG是一款适合对性能、功耗和接口灵活性有较高要求的应用的NOR闪存解决方案，适用于各种嵌入式系统和工业级设备。随着技术规格的不断更新，武汉新芯会持续优化这款产品的特性以满足市场需求。

This Data Sheet may be revised by subsequent versions Wuhan Xinxin Semiconductor Manufacturing Corp.

or modifications due to changes in technical specifications.

XM25QH128A

preliminary

Rev. H, Issue Date: 2018/08/06

Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and

a Page Program (PP) or Quad Input Page Program (QPP) sequence, which consists of four bytes plus

data. This is followed by the internal Program cycle (of duration t

To spread this overhead, the Page Program (PP) or Quad Input Page Program (QPP) instruction allows

up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in

consecutive addresses on the same page of memory.

Sector Erase, Half Block Erase, Block Erase and Chip Erase

The Page Program (PP) or Quad Input Page Program (QPP) instruction allows bits to be reset from 1 to

0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can

be achieved a sector at a time, using the Sector Erase (SE) instruction, half a block at a time using the

Half Block Erase (HBE) instruction, a block at a time using the Block Erase (BE) instruction or

throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle

(of duration t

SE,

HBE,,

or t

). The Erase instruction must be preceded by a Write Enable (WREN)

instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP, QPP) or Erase (SE,

HBE, BE or CE) can be achieved by not waiting for the worst case delay (t

, t

HBE

or t

). The

Write In Progress (WIP) bit is provided in the Status Register so that the application program can

monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is

complete.

Active Power, Stand-by Power and Deep Power-Down Modes

When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip

Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal

cycles have completed (Program, Erase, Write Status Register). The device then goes into the Stand-by

Power mode. The device consumption drops to I

CC1

The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down

Mode (DP) instruction) is executed. The device consumption drops further to I

CC2

. The device remains in

this mode until another specific instruction (the Release from Deep Power-down Mode and Read Device

ID (RDI) instruction) is executed.

All other instructions are ignored while the device is in the Deep Power-down mode. This can be used

as an extra software protection mechanism, when the device is not in active use, to protect the device

from inadvertent Write, Program or Erase instructions.

Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern the

XM25QH128A provides the following data protection mechanisms:

 Power-On Reset and an internal timer (t

PUW

) can provide protection against inadvertent changes

while the power supply is outside the operating specification.

 Program, Erase and Write Status Register instructions are checked that they consist of a number

of clock pulses that is a multiple of eight, before they are accepted for execution.

 All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the

Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:

– Power-up

– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction

completion or Page Program (PP), Quad Input Page Program (QPP) instruction completion

or Sector Erase (SE) instruction completion or Half Block Erase (HBE) / Block Erase (BE)

instruction completion or Chip Erase (CE) instruction completion

– Software/Hardware Reset completion

 The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-

only. This is the Software Protected Mode (SPM).

 The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status

 In addition to the low power consumption feature, the Deep Power-down mode offers extra

software protection from inadvertent Write, Program and Erase instructions, as all instructions are

ignored except one particular instruction (the Release from Deep Power-down instruction).

This Data Sheet may be revised by subsequent versions Wuhan Xinxin Semiconductor Manufacturing Corp.

or modifications due to changes in technical specifications.

XM25QH128A

preliminary

Rev. H, Issue Date: 2018/08/06

Table 3. Protected Area Sizes Sector Organization

Status Register Content

Memory Content

T/B

SR.5

SR.4

SR.3

SR.2

Protect Areas

Addresses

Density(KB)

Portion

Bit

None

Block 252 to 255

FC0000h-FFFFFFh

256KB

Upper 4/256

Block 248 to 255

F80000h-FFFFFFh

512KB

Upper 8/256

Block 240 to 255

F00000h-FFFFFFh

1024KB

Upper 16/256

Block 224 to 255

E00000h-FFFFFFh

2048KB

Upper 32/256

Block 192 to 255

C00000h-FFFFFFh

4096KB

Upper 64/256

Block 128 to 255

800000h-FFFFFFh

8192KB

Upper 128/256

Block 0 to 255

000000h-FFFFFFh

16384KB

All

None

Block 0 to 3

000000h-03FFFFh

256KB

Lower 4/256

Block 0 to 7

000000h-07FFFFh

512KB

Lower 8/256

Block 0 to 15

000000h-0FFFFFh

1024KB

Lower 16/256

Block 0 to 31

000000h-1FFFFFh

2048KB

Lower 32/256

Block 0 to 63

000000h-3FFFFFh

4096KB

Lower 64/256

Block 0 to 127

000000h-7FFFFFh

8192KB

Lower 128/256

Block 0 to 255

000000h-FFFFFFh

16384KB

All

None

Block 0 to 251

000000h-FBFFFFh

16128KB

Lower 252/256

Block 0 to 247

000000h-F7FFFFh

15872KB

Lower 248/256

Block 0 to 239

000000h-EFFFFFh

15360KB

Lower 240/256

Block 0 to 223

000000h-DFFFFFh

14336KB

Lower 224/256

Block 0 to 191

000000h-BFFFFFh

12288KB

Lower 192/256

Block 0 to 127

000000h-7FFFFFh

8192KB

Lower 128/256

Block 0 to 255

000000h-FFFFFFh

16384KB

All

None

Block 4 to 255

040000h-FFFFFFh

16128KB

Upper 252/256

Block 8 to 255

080000h-FFFFFFh

15872KB

Upper 248/256

Block 16 to 255

100000h-FFFFFFh

15360KB

Upper 240/256

Block 32 to 255

200000h-FFFFFFh

14336KB

Upper 224/256

Block 64 to 255

400000h-FFFFFFh

12288KB

Upper 192/256

Block 128 to 255

800000h-FFFFFFh

8192KB

Upper 128/256

Block 0 to 255

000000h-FFFFFFh

16384KB

All

This Data Sheet may be revised by subsequent versions Wuhan Xinxin Semiconductor Manufacturing Corp.

or modifications due to changes in technical specifications.

XM25QH128A

preliminary

Rev. H, Issue Date: 2018/08/06

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial

Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven

Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on

Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code.

Depending on the instruction, it might be followed by address bytes, or data bytes, or both or none. Chip

Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the

case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Dual Output Fast

Read (3Bh), Dual I/O Fast Read (BBh), Quad Output Fast Read (6Bh), Quad Input/Output FAST_READ

(EBh), Read Status Register (RDSR), Read Suspend Status Register (RDSSR) or Release from Deep

Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a

data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being

shifted out.

In the case of a write instruction, Chip Select (CS#) must be driven High exactly at a byte boundary,

otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High

when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight.

For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be

reset.

In the case of multi-byte commands of Page Program (PP), Quad Input Page Program (QPP), and

Release from Deep Power Down (RES ) minimum number of bytes specified has to be given,

without which, the command will be ignored.

In the case of Page Program, if the number of byte after the command is less than 4 (at least 1

data byte), it will be ignored too. In the case of SE and HBE / BE, exact 24-bit address is a must,

any less or more will cause the command to be ignored.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase

cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues

unaffected.

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