TRINAMIC TMC2209电机驱动芯片详细规格与应用

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C465949-《TMC2209-LA电机驱动芯片规格书》是由德国Trinamic Motion Control GmbH & Co. KG公司提供的技术文档。这份规格书详述了TMC2209/TMC2226系列电机驱动芯片的主要特性、应用领域及优势。 TMC2209是一款针对步进电机设计的高性能驱动芯片，特别适合于高电流需求（峰值可达2.8A，每相2A），支持接口灵活，可以设置8、16、32或64微步，提供了MicroPlyer™技术，使得在256微步模式下运行更加平滑。 StealthChop2™功能使得电机在低噪音状态下工作，适用于对静音性能要求高的场合，如3D打印机和办公室自动化设备。这款芯片采用了SpreadCycle™动态电机控制技术，能实现高效能的电机操作。StallGuard4™功能可以检测负载和电机锁定状态，确保在遇到这些问题时自动调整，保护电机免受损坏，并保持 StealthChop 的无声效果。 CoolStep™电流控制技术有助于节省高达75%的能源，使得该芯片在电池供电或需符合能效标准（如欧盟规定）的设备上表现出色。其低RDSon值（典型情况下，低阻态耗散为170mΩ）和低热升特性，有助于降低芯片发热并延长使用寿命。电压范围宽广，支持4.75V到29V直流电源，同时提供低功耗待机模式，适合电池供电设备。TMC2209还内置了内部传感器电阻选项，无需外部附加元件，简化了设计。它具备被动制动、自由轮和自动功率管理功能，提高了系统的整体效率。此外，TMC2209支持单线UART通信以及One-Time Programmable (OTP)功能，为高级配置提供了更多可能性。集成的脉冲发生器使其能够独立进行运动控制，且具有全面的保护和诊断功能，确保系统稳定可靠。最后，TMC2209芯片有QFN和HTSS两种封装选择，以适应不同的应用环境和尺寸要求。总体来说，这款驱动芯片凭借其出色的性能、广泛的兼容性和易于集成的特点，是电机驱动领域的理想解决方案，尤其适用于打印、办公自动化、纺织机械、安防监控等领域中的高精度、低噪声和节能设备。

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While the standard application circuit is limited to roughly 5.2 V lower supply voltage, a 5 V only

application lets the IC run from a 5 V +/-5% supply. In this application, linear regulator drop must be

minimized. Therefore, the internal 5V regulator is filtered with a higher capacitance. An optional

resistor bridges the internal 5V regulator by connecting 5VOUT to the external power supply. This RC

filter keeps chopper ripple away from 5VOUT. With this resistor, the external supply is the reference

for the absolute motor current and must not exceed 5.5V. Standby function will not work in this

application, because the 5V regulator is bridged.

3.4 Configuration Pins

The TMC22xx family members provide three or four configuration pins depending on the package

option. These pins allow quick configuration for standalone operation. Several additional options can

be set by OTP programming. In UART mode, the configuration pins can be disabled in order to set a

different configuration via registers.

PDN_UART: CONFIGURATION OF STANDSTILL POWER DOWN

PDN_UART

Current Setting

GND

Enable automatic power down in standstill periods

VCC_IO

Disable

UART interface

When using the UART interface, the configuration pin should be disabled via

GCONF.pdn_disable = 1. Program IHOLD as desired for standstill periods.

MS1/MS2: CONFIGURATION OF MICROSTEP RESOLUTION FOR STEP INPUT

MS2

MS1

Microstep Setting

GND

8 microsteps

GND

VCC_IO

32 microsteps (different to TMC2208!)

VCC_IO

GND

64 microsteps (different to TMC2208!)

VCC_IO

16 microsteps

SPREAD: SELECTION OF CHOPPER MODE

SPREAD

Chopper Setting

GND or

Pin open / not

available

StealthChop is selected. Automatic switching to SpreadCycle in dependence of

the step frequency can be programmed via OTP.

VCC_IO

SpreadCycle operation.

3.5 High Motor Current

When operating at a high motor current, the driver power dissipation due to MOSFET switch on-

resistance significantly heats up the driver. This power dissipation will significantly heat up the PCB

cooling infrastructure, if operated at an increased duty cycle. This in turn leads to a further increase of

driver temperature. An increase of temperature by about 100°C increases MOSFET resistance by

roughly 50%. This is a typical behavior of MOSFET switches. Therefore, under high duty cycle, high

load conditions, thermal characteristics have to be carefully taken into account, especially when

increased environment temperatures are to be supported. Refer the thermal characteristics and the

layout hints for more information. As a thumb rule, thermal properties of the PCB design become

critical for the tiny QFN 5mm x 5mm package at or above 1.4A RMS motor current for increased

periods of time. Keep in mind that resistive power dissipation rises with the square of the motor

current. On the other hand, this means that a small reduction of motor current significantly saves heat

dissipation and energy.

Pay special attention to good thermal properties of your PCB layout, when going for 1.4A RMS current

or more.

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An effect which might be perceived at medium motor velocities and motor sine wave peak currents

above roughly 2A peak is a slight sine distortion of the current wave when using SpreadCycle. It

results from an increasing negative impact of parasitic internal diode conduction, which in turn

negatively influences the duration of the fast decay cycle of the SpreadCycle chopper. This is, because

the current measurement does not see the full coil current during this phase of the sine wave,

because an increasing part of the current flows directly from the power MOSFETs’ drain to GND and

does not flow through the sense resistor. This effect with most motors does not negatively influence

the smoothness of operation, as it does not impact the critical current zero transition. The effect does

not occur with StealthChop.

3.6 Low Power Standby

Battery powered applications, and mains powered applications conforming to standby energy saving

rules, often require a standby operation, where the power-supply remains on, but current draw goes

down to a low value. The TMC2209/2226 support standby operation of roughly 2mW (at 12V supply),

or <1mW at 5V supply using a dedicated pin STANDYBY. Pull up STANDBY to VCC_IO to go to low

power standby. VCC_IO may be dropped down to 1.5V during standby. A high level on STANDBY will

disable the internal 5V regulator and at the same time switches off all internal units. Prior to going to

STANDBY, stop the motor, and allow it to enter standstill current, or switch off the motor completely.

When in STANDBY, inputs ENN and VREF have to be driven to a low level. VCC_IO shall remain active

in standby mode. All driver registers are reset to their power-up defaults after leaving standby mode.

3.7 Driver Protection and EME Circuitry

Some applications have to cope with ESD events caused by motor operation or external influence.

Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset

or even a destruction of the motor driver, depending on their energy. Especially plastic housings and

belt drive systems tend to cause ESD events of several kV. It is best practice to avoid ESD events by

attaching all conductive parts, especially the motors themselves to PCB ground, or to apply electrically

conductive plastic parts. In addition, the driver can be protected up to a certain degree against ESD

events or live plugging / pulling the motor, which also causes high voltages and high currents into

the motor connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the

dV/dt caused by ESD events. Larger capacitors will bring more benefit concerning ESD suppression,

but cause additional current flow in each chopper cycle, and thus increase driver power dissipation,

especially at high supply voltages. The values shown are example values – they may be varied

between 100pF and 1nF. The capacitors also dampen high frequency noise injected from digital parts

of the application PCB circuitry and thus reduce electromagnetic emission. A more elaborate scheme

uses LC filters to de-couple the driver outputs from the motor connector. Varistors in between of the

coil terminals eliminate coil overvoltage caused by live plugging. Optionally protect all outputs by a

varistor to GND against ESD voltage.

Full Bridge A

Full Bridge B

stepper

motor

OA1

OA2

OB1

OB2

Driver

470pF

100V

470pF

100V

470pF

100V

470pF

100V

Full Bridge A

Full Bridge B

stepper

motor

OA1

OA2

OB1

OB2

Driver

470pF

100V

470pF

100V

50Ohm @

100MHz

50Ohm @

100MHz

50Ohm @

100MHz

50Ohm @

100MHz

Fit varistors to supply voltage

rating. SMD inductivities

conduct full motor coil

current.

470pF

100V

470pF

100V

Varistors V1 and V2 protect

against inductive motor coil

overvoltage.

V1A, V1B, V2A, V2B:

Optional position for varistors

in case of heavy ESD events.

BRB

BRA

100nF

16V

100nF

16V

V1A

V1B

V2A

V2B

Figure 3.4 Simple ESD enhancement and more elaborate motor output protection

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4 UART Single Wire Interface

The UART single wire interface allows control of the TMC22xx with any microcontroller UART. It shares

transmit and receive line like an RS485 based interface. Data transmission is secured using a cyclic

redundancy check, so that increased interface distances (e.g. over cables between two PCBs) can be

bridged without danger of wrong or missed commands even in the event of electro-magnetic

disturbance. The automatic baud rate detection makes this interface easy to use.

4.1 Datagram Structure

4.1.1 Write Access

UART WRITE ACCESS DATAGRAM STRUCTURE

each byte is LSB…MSB, highest byte transmitted first

0 … 63

sync + reserved

8 bit slave

address

RW + 7 bit

32 bit data

CRC

0…7

8…15

16…23

24…55

56…63

Reserved (don’t cares

but included in CRC)

SLAVEADDR=0…3

address

data bytes 3, 2, 1, 0

(high to low byte)

CRC

…

A sync nibble precedes each transmission to and from the TMC22xx and is embedded into the first

transmitted byte, followed by an addressing byte (0 to 3 for TMC22xx, depending on address setting).

Each transmission allows a synchronization of the internal baud rate divider to the master clock. The

actual baud rate is adapted and variations of the internal clock frequency are compensated. Thus, the

baud rate can be freely chosen within the valid range. Each transmitted byte starts with a start bit

(logic 0, low level on SWIOP) and ends with a stop bit (logic 1, high level on SWIOP). The bit time is

calculated by measuring the time from the beginning of start bit (1 to 0 transition) to the end of the

sync frame (1 to 0 transition from bit 2 to bit 3). All data is transmitted bytewise. The 32 bit data

words are transmitted with the highest byte first.

A minimum baud rate of 9000 baud is permissible, assuming 20 MHz clock (worst case for low baud

rate). Maximum baud rate is f

CLK

/16 due to the required stability of the baud clock.

The slave address SLAVEADDR is selected by MS1 (bit 0) and MS2 (bit 1).

The communication becomes reset if a pause time of longer than 63 bit times between the start bits

of two successive bytes occurs. This timing is based on the last correctly received datagram. In this

case, the transmission needs to be restarted after a failure recovery time of minimum 12 bit times of

bus idle time. This scheme allows the master to reset communication in case of transmission errors.

Any pulse on an idle data line below 16 clock cycles will be treated as a glitch and leads to a timeout

of 12 bit times, for which the data line must be idle. Other errors like wrong CRC are also treated the

same way. This allows a safe re-synchronization of the transmission after any error conditions.

Remark, that due to this mechanism an abrupt reduction of the baud rate to less than 15 percent of

the previous value is not possible.

Each accepted write datagram becomes acknowledged by the receiver by incrementing an internal

cyclic datagram counter (8 bit). Reading out the datagram counter allows the master to check the

success of an initialization sequence or single write accesses. Read accesses do not modify the

counter.

UART

TMC2209, TMC2226 DATASHEET (Rev. 1.02 / 2019-MAY-14) 17

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The UART line must be logic high during idle state. Therefore, the power down function cannot be

assigned by the pin PDN_UART in between of transmissions. In an application using the UART

interface, set the desired power down function by register access and set pdn_disable in GCONF to

disable the pin function.

4.1.2 Read Access

UART READ ACCESS REQUEST DATAGRAM STRUCTURE

each byte is LSB…MSB, highest byte transmitted first

sync + reserved

8 bit slave address

RW + 7 bit register

address

CRC

0...7

8…15

16…23

24…31

Reserved (don’t cares

but included in CRC)

SLAVEADDR=0…3

CRC

…

The read access request datagram structure is identical to the write access datagram structure, but

uses a lower number of user bits. Its function is the addressing of the slave and the transmission of

the desired register address for the read access. The TMC22xx responds with the same baud rate as

the master uses for the read request.

In order to ensure a clean bus transition from the master to the slave, the TMC22xx does not

immediately send the reply to a read access, but it uses a programmable delay time after which the

first reply byte becomes sent following a read request. This delay time can be set in multiples of

eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the

master.

UART READ ACCESS REPLY DATAGRAM STRUCTURE

each byte is LSB…MSB, highest byte transmitted first

0 ...... 63

sync + reserved

8 bit master

address

RW + 7 bit

32 bit data

CRC

0…7

8…15

16…23

24…55

56…63

reserved (0)

0xFF

address

data bytes 3, 2, 1, 0

(high to low byte)

CRC

…

The read response is sent to the master using address code %11111111. The transmitter becomes

switched inactive four bit times after the last bit is sent.

Address %11111111 is reserved for read access replies going to the master.

TMC2209, TMC2226 DATASHEET (Rev. 1.02 / 2019-MAY-14) 18

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4.2 CRC Calculation

An 8 bit CRC polynomial is used for checking both read and write access. It allows detection of up to

eight single bit errors. The CRC8-ATM polynomial with an initial value of zero is applied LSB to MSB,

including the sync- and addressing byte. The sync nibble is assumed to always be correct. The

TMC22xx responds only to correctly transmitted datagrams containing its own slave address. It

increases its datagram counter for each correctly received write access datagram.

𝐶𝑅𝐶=𝑥

+𝑥

SERIAL CALCULATION EXAMPLE

CRC = (CRC << 1) OR (CRC.7 XOR CRC.1 XOR CRC.0 XOR [new incoming bit])

C-CODE EXAMPLE FOR CRC CALCULATION

void swuart_calcCRC(UCHAR* datagram, UCHAR datagramLength)

{

int i,j;

UCHAR* crc = datagram + (datagramLength-1); // CRC located in last byte of message

UCHAR currentByte;

*crc = 0;

for (i=0; i<(datagramLength-1); i++) { // Execute for all bytes of a message

currentByte = datagram[i]; // Retrieve a byte to be sent from Array

for (j=0; j<8; j++) {

if ((*crc >> 7) ^ (currentByte&0x01)) // update CRC based result of XOR operation

{

*crc = (*crc << 1) ^ 0x07;

}

else

{

*crc = (*crc << 1);

}

currentByte = currentByte >> 1;

} // for CRC bit

} // for message byte

}

4.3 UART Signals

The UART interface on the TMC22xx uses a single bi-direction pin:

UART INTERFACE SIGNAL

PDN_UART

Non-inverted data input and output. I/O with Schmitt Trigger and VCC_IO level.

MS1_ADDR0

IC UART address bit 0 (LSB)

MS2_ADDR1

IC UART address bit 1

The IC checks PDN_UART for correctly received datagrams with its own address continuously. It adapts

to the baud rate based on the sync nibble, as described before. In case of a read access, it switches

on its output drivers and sends its response using the same baud rate. The output becomes switched

off four bit times after transfer of the last stop bit.

Master CPU

(µC with UART)

TMC22xx

different address

(R/W access)

PDN_UART

TXD

RXD

Master CPU

(µC with UART)

TMC22xx #1

same address

(write only access)

PDN_UART

TXD

TMC22xx #2

same address

(write only access)

PDN_UART

TMC22xx

different address

(R/W access)

PDN_UART

MS2_AD1

MS1_AD0

MS2_AD1

MS1_AD0

CCIO

Figure 4.1 Attaching the TMC22xx to a microcontroller UART

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