TLV320ADC3101: 低功耗立体声ADC与嵌入式miniDSP

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"TI-TLV320ADC3101.pdf 是一款由TI（德州仪器）推出的低功耗立体声模拟到数字转换器（ADC），适用于无线手机和便携式音频系统，具有内置的迷你DSP（数字信号处理器）功能。" **TLV320ADC3101关键特性：** 1. **立体声音频ADC** - 提供高质量的立体声音频转换。 2. **无线手机应用** - 专为无线通信设备设计，适应其低功耗需求。 3. **便携式低功耗音频系统** - 优化了能源效率，适合便携设备。 4. **92-dB信噪比** - 高信噪比确保了音频信号的清晰度和纯净度。 5. **支持多种采样率** - 从8kHz到96kHz，适应不同应用场景。 6. **前端语音或音频处理器** - 适用于数字音频处理。 7. **指令可编程嵌入式迷你DSP** - 可根据需求定制处理算法。 8. **灵活的数字滤波** - 支持低延迟IIR滤波器（用于语音）和线性相位FIR滤波器（用于音频）。 9. **可编程增益放大器** - 提供高达40dB的模拟增益或自动增益控制（AGC）。 **应用领域：** 1. **无线手机** - 用于手机中的音频处理和录音。 2. **噪声消除系统** - 利用内置的DSP进行噪声过滤和消除。 3. **便携式低功耗音频系统** - 如蓝牙音箱、MP3播放器等。 4. **数字音频前端处理** - 在各种音频设备中提供预处理功能。 **描述与功能模块：** - **低延迟IIR滤波器** - 实时处理语音信号，减少响应时间，提高通话质量。 - **线性相位FIR滤波器** - 用于音频处理，确保在不同频率上保持一致的时间延迟，提高音质。 - **可编程系数、指令和内置处理** - 用户可以通过编程改变滤波器参数，实现不同的信号处理效果。 - **RAM可编程块** - 允许用户存储自定义的滤波器系数和处理程序，增加了灵活性。 **资源与支持：** 该产品附带了技术文档、工具软件、支持社区和参考设计，方便开发人员进行设计集成和优化。 TLV320ADC3101是一款高度集成的音频解决方案，结合了高精度的ADC和强大的迷你DSP，适用于需要高效能音频处理且对功耗有严格要求的无线和便携设备。通过其丰富的接口（如I2S、LJ、RJ、DSP和TDM），可以轻松与其他处理器和系统组件集成，实现复杂音频系统的构建。

LD(n)

LD(n+1)

WORD

CLOCK

BIT

CLOCK

DATA

RD(n)

LEFT CHANNEL RIGHT CHANNEL

LD(n) = nth Sample of Left-Channel Data RD(n) = nth Sample of Right-Channel Data

2 1 03 2 1 03

n-3

n-1 n-2 n-3n-1 n-2

n-3n-1 n-2

BCLK

WCLK

DIN/

DOUT

n-1 n-2 1 00 n-1 n-2 1 0

1/fs

LSBMSB

LeftChannel RightChannel

n-3 2 2n-3

LSBMSB

TLV320ADC3101

SLAS553B –NOVEMBER 2008–REVISED AUGUST 2015

www.ti.com

Feature Description (continued)

By default, when the word clocks and bit clocks are generated by the TLV320ADC3101, these clocks are active

only when the ADC is powered up within the device. This is done to save power. However, it also supports a

feature wherein both the word clocks and bit clocks can be active even when the codec in the device is powered

down. This is useful when using the TDM mode with multiple codecs on the same bus or when word clocks or bit

clocks are used in the system as general-purpose clocks.

10.3.6.1 Right-Justified Mode

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling

edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding

the rising edge of the word clock. See Figure 13 for right-justifed mode timing.

Figure 13. Timing Diagram for Right-Justified Mode

For right-justified mode, the number of bit clocks per frame must be greater than twice the programmed word-

length of the data.

NOTE

The time-slot-based mode is not available in the right-justified mode.

10.3.6.2 Left-Justified Mode

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling

edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following

the rising edge of the word clock. Figure 14 shows the standard timing of the left-justified mode.

Figure 14. Left-Justified Mode (Standard Timing)

Figure 15 shows the left-justified mode with Ch_Offset_1 = 1.

Product Folder Links: TLV320ADC3101

LD (n) LD(n+1)RD (n)

2 1

3 3

LEFT CHANNEL RIGHT CHANNEL

LD(n) = nth Sample of Left-Channel Data RD(n) = nth Sample of Right-Channel Data

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2

n-3

n-1 n-2

n-3

n-1 n-2

n-3

Ch_Offset_1 = 0

2 1

LD(n) LD(n+1)

2 1

RD(n)

LEFT CHANNEL RIGHT CHANNEL

LD(n) = nth Sample of Left-Channel Data RD(n) = nth Sample of Right-Channel Data

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2

n-3

n-1 n-2

n-3

n-1 n-2

n-3

Ch_Offset_1 = 1

TLV320ADC3101

www.ti.com

SLAS553B –NOVEMBER 2008–REVISED AUGUST 2015

Feature Description (continued)

Figure 15. Left-Justified Mode With Ch_Offset_1 = 1

Figure 16 shows the left-justified mode with Ch_Offset_1 = 0 and bit clock inverted.

Figure 16. Left-Justified Mode With Ch_Offset_1 = 0, Bit Clock Inverted

For left-justified mode, the number of bit clocks per frame must be greater than twice the programmed word

length of the data. Also, the programmed offset value must be less than the number of bit clocks per frame by at

least the programmed word length of the data.

When the time-slot-based channel assignment is disabled (page 0 / register 38, bit D0 = 0), the left and right

channels have the same offset Ch_Offset_1 (page 0 / register 28), and each edge of the word clock starts data

transfer for one of the two channels, depending on whether or not channel swapping is enabled. Data bits are

valid on the rising edges of the bit clock. With the time-slot-based channel assignment enabled (page 0 / register

38, bit D0 = 1), the left and right channels have independent offsets (Ch_Offset_1 and Ch_Offset_2). The rising

edge of the word clock starts data transfer for the first channel after a delay of its programmed offset

(Ch_Offset_1) for this channel. Data transfer for the second channel starts after a delay of its programmed offset

(Ch_Offset_2) from the LSB of the first-channel data. The falling edge of the word clock is not used.

With no channel swapping, the MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit

clock following the rising edge of the word clock. And, the MSB of the right channel is valid on the (Ch_Offset_1

+ 1)th rising edge of the bit clock following the falling edge of the word clock. The operation in this case, with

offset of 1, is shown in the timing diagram of Figure 15. Because channel swapping is not enabled, the left-

channel data is before the right-channel data. With channel swapping enabled, the MSB of the right channel is

valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And, the

MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the falling edge

of the word clock. The operation in this case, with offset of 1, is shown in the timing diagram of Figure 17. As

shown in the diagram, right-channel data of a frame is before that frame’s left-channel data, due to channel

swapping. Otherwise, the behavior is similar to the case where channel swapping is disabled. The MSB of the

right-channel data is valid on the second rising edge of the bit clock after the rising edge of the word clock, due

to an offset of 1. Similarly, the MSB of the left-channel data is valid on the second rising edge of the bit clock

after the falling edge of the word clock.

Product Folder Links: TLV320ADC3101

LD (n)

LD(n+1)

2 1

RD (n)

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2

n-3

n-1 n-2

n-3

n-1 n-2

n-3

Left Channel Right Channel

Ch_Offset_1 = 0 Ch_Offset_2 = 1

RD(n)

RD(n+1)

2 1

LD(n)

RIGHT CHANNEL LEFT CHANNEL

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2

n-3

n-1 n-2

n-3

n-1 n-2

n-3

Ch_Offset_1 = 1 Ch_Offset_1 = 1

TLV320ADC3101

SLAS553B –NOVEMBER 2008–REVISED AUGUST 2015

www.ti.com

Feature Description (continued)

Figure 17. Left-Justified Mode With Ch_Offset_1 = 1, Channel Swapping Enabled

When time-based-slot mode is enabled with no channel swapping, the MSB of the left channel is valid on the

(Offset1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And, the MSB of the right

channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the left channel.

Figure 18 shows the operation with time-based-slot mode enabled and Ch_Offset_1 = 0 and Ch_Offset_2 = 1.

The MSB of the left channel is valid on the first rising edge of the bit clock after the rising edge of the word clock.

Data transfer for the right channel does not wait for the falling edge of the word clock, and the MSB of the right

channel is valid on the second rising edge of the bit clock after the LSB of the left channel.

Figure 18. Left-Justified Mode, Time-Based-Slot Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1

For the case with time-based-slot mode enabled and channel swapping enabled, the MSB of the right channel is

valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And, the

MSB of the left channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the

right channel. Figure 19 shows the operation in this mode with Ch_Offset_1 = 0 and Ch_Offset_2 = 1. The MSB

of the right channel is valid on the first rising edge of the bit clock after the rising edge of the word clock. Data

transfer for the left channel starts following the completion of data transfer for the right channel without waiting for

the falling edge of the word clock. The MSB of the left channel is valid on the second rising edge of the bit clock

after the LSB of the right channel.

Product Folder Links: TLV320ADC3101

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