I2C协议规范 V2.1详解：设计者与制造商的福音

协议规范

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"I2C协议规范 V2.1 JANUARY 2000" I2C（Inter-Integrated Circuit）协议是一种由飞利浦半导体（现为恩智浦半导体）开发的简单、高效的两线式串行通信总线，用于连接微控制器和其他设备。这个协议规范V2.1于1990年1月发布，主要服务于信号测试和电子工程（EE）领域。 1. **版本历史** - 版本1.0：1992年发布，标志着I2C协议的初步形成。 - 版本2.0：1983年更新，对协议进行了扩展和完善。 - 版本2.1：1999年更新，进一步优化了协议功能，以适应不断发展的电子技术需求。 2. **设计者与制造商的优势** - 设计者优势：I2C协议简化了硬件设计，降低了系统复杂性，减少了所需引脚数量，同时提供了一种标准化的通信方式。 - 制造商优势：通过使用I2C，制造商可以降低成本，提高产品的互操作性和兼容性。 3. **I2C总线概念** I2C总线是一种多主控、单向数据传输的总线，它包含两条线：一条数据线（SDA）和一条时钟线（SCL），用于同步数据传输。 4. **基本特性** I2C协议定义了数据传输的开始和停止条件、数据有效性的规则，以及数据字节格式和应答机制。 5. **位传输** - 数据有效性：在时钟脉冲的高电平期间，数据线上的数据位是有效的。 - 开始和停止条件：开始条件是SCL为高时SDA线由高变低，停止条件则是SDA线在SCL为高时由低变高。 6. **数据传输** - 字节格式：每个传输的字节包含8位数据，最高位（MSB）先发送。 - 应答：每个接收的字节后，接收方会通过拉低SDA线进行应答，表示数据已接收。 7. **仲裁与时钟生成** - 同步：所有设备都基于相同的时钟进行操作，确保数据传输的一致性。 - 仲裁：在多个主控器同时尝试控制总线时，通过比较SDA线上数据位来决定哪个主控器继续传输。 - 时钟同步机制作为握手：主控器可以通过调整时钟频率来协调与其他设备的数据交换。 8. **7位地址格式** - 标准的I2C传输使用7位地址来标识目标设备，允许最多128个不同的设备连接到同一总线。 - 第一个字节的高位定义了地址，低四位用于控制读写操作。 - 包含通用呼叫地址、启动字节和兼容CBUS的特殊考虑。 9. **扩展模式** - 标准模式：基础的I2C协议，支持较低的数据传输速率。 - 快速模式：速度更快，支持高达400kHz的数据传输速率。 - 高速模式（Hs-Mode）：进一步提升传输速率，可达3.4MHz，适用于高速数据传输应用。 I2C协议因其简洁性和灵活性，在嵌入式系统和消费电子产品中广泛使用，从微控制器到传感器，再到显示模块，都可能通过I2C进行通信。通过理解和掌握I2C协议，开发者可以有效地构建高效、低功耗的系统。

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Philips Semiconductors

The I

C-bus specification

Generation of clock signals on the I

C-bus is always the

responsibility of master devices; each master generates its

own clock signals when transferring data on the bus. Bus

clock signals from a master can only be altered when they

are stretched by a slow-slave device holding-down the

clock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to a

positive supply voltage via a current-source or pull-up

resistor (see Fig.3). When the bus is free, both lines are

HIGH. The output stages of devices connected to the bus

must have an open-drain or open-collector to perform the

wired-AND function. Data on the I

C-bus can be

transferred at rates of up to 100 kbit/s in the

Standard-mode, up to 400 kbit/s in the Fast-mode, or up to

3.4 Mbit/s in the High-speed mode. The number of

interfaces connected to the bus is solely dependent on the

bus capacitance limit of 400 pF. For information on

High-speed mode master devices, see Section 13.

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,

NMOS, bipolar) which can be connected to the I

C-bus,

the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not

fixed and depend on the associated level of V

(see

Section 15 for electrical specifications). One clock pulse is

generated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW (see Fig.4).

Fig.3 Connection of Standard- and Fast-mode devices to the I

C-bus.

MBC631

SCLKN1

OUT

SCLK

DATAN1

OUT

DATA

DEVICE 1

SDA (Serial Data Line)

SCL (Serial Clock Line)

SCLKN2

OUT

SCLK

DATAN2

OUT

DATA

DEVICE 2

pull-up

resistors

Philips Semiconductors

The I

C-bus specification

7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most

significant bit (MSB) first (see Fig.6). If a slave can’t

receive or transmit another complete byte of data until it

has performed some other function, for example servicing

an internal interrupt, it can hold the clock line SCL LOW to

force the master into a wait state. Data transfer then

continues when the slave is ready for another byte of data

and releases clock line SCL.

In some cases, it’s permitted to use a different format from

the I

C-bus format (for CBUS compatible devices for

example). A message which starts with such an address

can be terminated by generation of a STOP condition,

even during the transmission of a byte. In this case, no

acknowledge is generated (see Section 10.1.3).

7.2 Acknowledge

Data transfer with acknowledge is obligatory. The

acknowledge-related clock pulse is generated by the

master. The transmitter releases the SDA line (HIGH)

during the acknowledge clock pulse.

The receiver must pull down the SDA line during the

acknowledge clock pulse so that it remains stable LOW

during the HIGH period of this clock pulse (see Fig.7). Of

course, set-up and hold times (specified in Section 15)

must also be taken into account.

Usually, a receiver which has been addressed is obliged to

generate an acknowledge after each byte has been

received, except when the message starts with a CBUS

address (see Section 10.1.3).

When a slave doesn’t acknowledge the slave address (for

example, it’s unable to receive or transmit because it’s

performing some real-time function), the data line must be

left HIGH by the slave. The master can then generate

either a STOP condition to abort the transfer, or a repeated

START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address

but, some time later in the transfer cannot receive any

more data bytes, the master must again abort the transfer.

This is indicated by the slave generating the

not-acknowledge on the first byte to follow. The slave

leaves the data line HIGH and the master generates a

STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal

the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out of

the slave. The slave-transmitter must release the data line

to allow the master to generate a STOP or repeated

START condition.

Fig.6 Data transfer on the I

C-bus.

handbook, full pagewidth

MSC608

SDA

SCL

STOP or

repeated START

condition

START or

repeated START

condition

1 2 3 - 8 9

ACK

7812

MSB

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

acknowledgement

signal from receiver

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