SPECTEK Confidential and Proprietary
LPDDR4/LPDDR4X SDRAM
Features
DQ Rx Voltage and Timing ......................................................................................................................................................... 277
Clock Specification ...................................................................................................................................................................... 280
t
CK(abs),
t
CH(abs), and
t
CL(abs) ........................................................................................................................................... 281
Clock Period Jitter ........................................................................................................................................................................ 281
Clock Period Jitter Effects on Core Timing Parameters .......................................................................................................... 281
Cycle Time Derating for Core Timing Parameters .................................................................................................................. 282
Clock Cycle Derating for Core Timing Parameters ................................................................................................................ 282
Clock Jitter Effects on Command/Address Timing Parameters .............................................................................................. 282
Clock Jitter Effects on READ Timing Parameters .................................................................................................................. 282
Clock Jitter Effects on WRITE Timing Parameters ................................................................................................................ 283
LPDDR4 1.10V V
DDQ
........................................................................................................................................................................ 284
Power-Up and Initialization - LPDDR4 .................................................................................................................................. 284
Mode Register Definition - LPDDR4 ...................................................................................................................................... 285
Burst READ Operation - LPDDR4 ATE Condition ................................................................................................................ 294
t
LZ(DQS),
t
LZ(DQ),
t
HZ(DQS),
t
HZ(DQ) Calculation........................................................................................................................
294
t
LZ(DQS) and
t
HZ(DQS) Calculation for ATE (Automatic Test Equipment) ......................................................................................
294
t
LZ(DQ) and
t
HZ(DQ) Calculation for ATE (Automatic Test Equipment) ....................................................................... 296
V
REF
Specifications - LPDDR4 ................................................................................................................................................................. 298
Internal V
REF(CA)
Specifications ........................................................................................................................................................ 298
Internal V
REF(DQ)
Specifications ........................................................................................................................................................ 299
Command Definitions and Timing Diagrams - LPDDR4 ....................................................................................................... 301
Pull Up/Pull Down Driver Characteristics and Calibration ................................................................................................ 301
On-Die Termination for the Command/Address Bus ......................................................................................................... 301
ODT Mode Register and ODT State Table......................................................................................................................... 302
ODT Mode Register and ODT Characteristics ................................................................................................................... 303
DQ On-Die Termination ..................................................................................................................................................... 304
Output Driver and Termination Register Temperature and Voltage Sensitivity................................................................. 307
AC and DC Operating Conditions - LPDDR4 ........................................................................................................................ 308
Recommended DC Operating Conditions .......................................................................................................................... 308
Output Slew Rate and Overshoot/Undershoot specifications - LPDDR4 ................................................................................ 308
Single-Ended Output Slew Rate ......................................................................................................................................... 308
Differential Output Slew Rate ............................................................................................................................................ 309
LVSTL I/O System - LPDDR4 ............................................................................................................................................... 310
Revision History .......................................................................................................................................................................... 312
Rev. C – 1/19 ........................................................................................................................................................................... 312
Rev. B – 10/18 ......................................................................................................................................................................... 312
Rev. A – 8/18 .......................................................................................................................................................................... 312
SPECTEK Technology, Inc. reserves the right to change products or specifications without notice.
z2bm_embedded_lpddr4_lpddr4x.pdf – Rev. C 1/19 EN
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