MATLAB仿真实现的MASH2-2 Sigma-Delta调制器设计

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"Mash2-2+Sigma-Delta调制器的设计及其MATLAB仿真_毕业论文.pdf" 这篇毕业论文深入探讨了MASH2-2 Sigma-Delta调制器的设计及其在MATLAB中的仿真方法。 Sigma-Delta调制器在现代信号处理和通信系统中广泛应用，因其能够在低分辨率硬件上实现高精度的信号转换而备受青睐。设计此类调制器时，平衡系统模拟时间和准确性是关键，尤其是在考虑实际非理想效应时。论文首先概述了MASH（多级噪声 shaping）2-2 Sigma-Delta调制器的基本概念。MASH结构是一种高级的Sigma-Delta调制形式，它通过多级噪声整形来提高系统的线性和动态范围。2-2表示该调制器具有两个第一阶Sigma-Delta模块串联，以形成一个第二阶的整体系统。这种设计可以有效地抑制噪声并增强系统性能。在论文中，作者构建了一个第四阶2-2 MASH Sigma-Delta调制器的行为模型，特别针对无线局域网（WLAN）应用。行为模型在MATLAB/SIMULINK环境中建立，这是一个强大的仿真工具，能够方便地进行复杂系统的设计和分析。该模型全面考虑了各种Sigma-Delta调制器的非理想因素，包括开关的热噪声、时钟抖动以及运算放大器的参数，如白噪声、有限直流增益、有限带宽、摆率和饱和电压。这些非理想特性对调制器的性能有显著影响，理解和模拟它们对于优化系统设计至关重要。通过MATLAB仿真，论文验证了所提模型的有效性。仿真结果表明，提出的模型在保持良好准确性的同时，也实现了快速的仿真速度，这对于提升系统性能和效率具有积极意义。这证明了MASH2-2 Sigma-Delta调制器在应对实际工程问题时的强大适应性和实用性。关键词：Sigma-Delta调制器，MASH调制器，MATLAB仿真，非理想效应，系统性能，运算放大器参数，无线局域网

Chapter 1 Introduction

values M which the ADC can produce at the output determines the resolution usually expressed in

number of bits N:

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(1.1)

Another parameter related to the amplitude discretization is the quantization step Δ which

is determined by (I.2) and represents the distance between adjacent levels. The size of the

quantization step Δ depends on the full scale of the input signal (V

min

< V < V

max

) and the number

of bits.

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





(1.2)

As consequence of the finite number of output values in a converter, errors into the digital

representation of the analog input are introduced.

These errors are called quantization errors e

and are illustrated in Figure 1.2. The range of

the quantization error in normal operation is –Δ/2 < e

< Δ/2, and usually is considered to have a

uniform probability density function within its range. Because of that, the quantization error can

be modelled as an additive white noise source, as shown in Figure 1.2 a, while the power spectral

density (PSD) in the range [-f

/2 to f

/2] is given by:

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

󰇜









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

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



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

 

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 



󰇢 







(1.3)

Two main groups of ADCs can be classified depending on the relationship between the

sampling frequency f

and the bandwidth (BW) of the input signal to be considered. The first group

are named Nyquist ADCs and their sampling frequencies follows the Nyquist theorem, where f

chosen to be equal to twice the signal bandwidth. While the second group are the Oversampling

ADCs in which the sampling frequency is higher than the previous case. The idea behind is to

crease the sampling frequency in order to trade it off with a significant reduction of the quantization

noise.

Chapter 1 Introduction

1.2 ADC architectures

The vast majority of ADC architectures used nowadays have been discovered and

published between the 40s and 60s [1]. Improvements in technology and in the optimization

processes have made possible to increase the performance.

The ADC could be classified in terms of resolution, speed of conversion, mode of

operation, internal structure, input/output type of signal, power consumption and others. The list

provided below reflects what is traditionally known for each type of ADC, however must not be

taken "as is" since research on this field is still very active, making the following distinctions more

and more blurry. In the following list the converters are classified in terms of speed of conversion

(form low to high speed of conversion versus the achievable resolution):

 Integrating ADC: Integration ADCs are characterized for having a low speed of conversion

and a high resolution. The idea behind this topology as the name suggest is the integration

of the signal during a period of time by means of a capacitor and discharging the mentioned

capacitor at a constant rate until is completely discharged. At that point knowing the two

times and the value of the voltage reference, is possible to know the value of the input

signal. The simplicity of this architecture makes them attractive for instrumental

applications and digital acquisition systems in which the speed of conversion is not a must.

 ΔΣ ADC : These ADCs are suited for low-mid conversion speeds and high resolution

applications. These converters are based on two concepts, one is the oversampling and the

other is the in-band noise shaping. The oversampling imposes a drawback in the frequency

of the input signal and therefore in the speed of conversion. Resolutions of 14 to 20 bits

are possible to be achieved with this architecture.

 SAR ADC: The Successive Approximation Register (SAR) ADC is suited for medium to

high resolutions, with speed in the range of few mega-samples per second. The typical

resolution achieved ranges between 8 to 16 bits maintaining a low power consumption and

a great noise figure. It is typical to use SAR ADC in portable electronics and data

acquisition systems.

Chapter 1 Introduction

 Pipeline ADC: Pipeline ADCs are used in applications with medium to high speed of

conversion and resolutions between 6 to 16 bits. It also has a good relation between speed-

resolution-consumption which is well suited for communication systems, image sensors

and digital video systems between others.

 Flash ADC: is the fastest ADC topology and it is used in high bandwidth applications. Its

main drawback is power consumption, resolution and manufacturing cost. In fact, this type

of ADC relies solely on the matching of electrical parameters that need to be trimmed (one

device at time) to accommodate for acceptable resolution. For this reason, they are

normally used in oscilloscopes, radars, satellites and other applications in which the speed

of conversion is a must. There is a topology in between the pipeline and the flash, called

Half-Flash which obtains a good relation between cost, speed and resolution which makes

them more competitive in signal processing applications.

1.3 Literature Review

Monolithic ADCs integration has evolved following a Moore-like law over nearly four

decades [1], thanks to the continuously increasing effort of the research community. ADC

performance has shown a remarkable improvement in many key parameters with respect to the

early days implementations. Low-power and small chip area are often pursued to allow the ADC

to be part of a larger system-on-chip (SoC). This trend has evolved from the early days in which

the major achievement was to implement a full converter in a single die with a modest speed and

resolution and a high power consumption. From a designer point of view, it is crucial to understand

the rate of performance and the roadmap of the different ADCs in order to be able to make the best

topology election for each application. Several authors have presented works that blend the

evolution surveys and derivations of theoretical physical limits to various degrees.

Historically, one of the most widely cited surveys is the Walden survey [2], which is one of

the pioneers and includes scientific and commercial ADC references from 1978 to 2008.

Nowadays, the Murmann survey is usually referenced [3]. This survey is continuously updated

and analyses ADC performance trends with a focus on energy per sample and signal to noise and

distortion ratio (SNDR). There are also other surveys based on different analysis of the ADC

performance [4] [5] [6] and different points of view [7].

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