Infineon Cypress USB3014 数据手册：EZ-USB FX3 超速USB控制器

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"赛普拉斯USB3014是一款由 Cypress Semiconductor Corporation 开发的高性能 USB 控制器，现属于 Infineon Technologies 公司的产品线。该数据手册详细介绍了 EZ-USB® FX3 超速 USB 控制器，它支持 USB 3.1 第一代（Gen1）和 USB 2.0 的外设集成。" 赛普拉斯USB3014数据手册主要涵盖以下关键知识点： 1. **产品背景**：Cypress Semiconductor Corporation 原先开发了这款产品，但随着 Cypress 成为 Infineon Technologies 公司的一部分，Infineon 将继续为新老客户提供该产品，确保产品阵容的连续性。 2. **文档内容连续性**：尽管产品所有权转移，但文档内容保持不变，未来如有修订，将在文档历史页面上更新，确保用户能获取准确的信息。 3. **订购部件编号**：Infineon 继续支持原有的部件编号，用户在订购时应继续使用数据手册中列出的订购部件编号。这确保了订购流程的顺畅性和一致性。 4. **产品名称**：CYUSB301X/CYUSB201X 是该系列产品的标识，其中 EZ-USB®FX3 是控制器的核心部分，专为实现 SuperSpeed USB 控制而设计。 5. **主要特性**： - **USB 集成**：USB3.1 Gen1 和 USB2.0 的兼容性使得该控制器能够与多种不同速度的 USB 设备无缝连接。 - **高速性能**：USB3.1 Gen1 提供高达 5 Gbps 的数据传输速率，显著提升设备间的通信速度。 - **通用性**：作为一款通用串行总线（Universal Serial Bus）控制器，它适用于各种应用，包括数据传输、设备控制等。 6. **制造商信息**：Cypress Semiconductor Corporation 的总部位于美国加利福尼亚州圣何塞，联系方式和相关网址也一并给出，便于用户获取更多信息或技术支持。 7. **文档版本**：数据手册的版本号为 001-52136 Rev.*X，修订日期为 2018 年 12 月 17 日，这意味着此手册可能有多个修订版，用户应使用最新的版本以获取最新信息。 8. **应用领域**：EZ-USB®FX3 控制器广泛应用于需要高速 USB 接口的各种电子产品中，如消费类电子、工业控制、医疗设备、数据存储和通信设备等。赛普拉斯USB3014数据手册提供了关于其功能、性能和使用方法的详尽指南，是设计和开发基于 USB 技术产品的工程师的重要参考资料。通过理解和应用这些知识点，开发者可以构建高效、可靠的 USB 解决方案。

CYUSB301X/CYUSB201X

Document Number: 001-52136 Rev. *X Page 9 of 58

UART Interface

The UART interface of FX3 supports full-duplex communication.

It includes the signals noted in Ta ble 1 .

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then FX3's UART only transmits data when the CTS

input is asserted. In addition to this, FX3’s UART asserts the RTS

output signal, when it is ready to receive data.

C Interface

FX3’s I

C interface is compatible with the I

C Bus Specification

Revision 3. This I

C interface is capable of operating only as I

master; therefore, it may be used to communicate with other I

slave devices. For example, FX3 may boot from an EEPROM

connected to the I

C interface, as a selectable boot option.

FX3’s I

C Master Controller also supports multi-master mode

functionality.

The power supply for the I

C interface is VIO5, which is a

separate power domain from the other serial peripherals. This

gives the I

C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The I

C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz. The I

C controller supports clock-stretching to

enable slower devices to exercise flow control.

The I

C interface’s SCL and SDA signals require external pull-up

resistors. The pull-up resistors must be connected to VIO5.

S Interface

FX3 has an I

S port to support external audio codec devices.

FX3 functions as I

S Master as transmitter only. The I

S interface

consists of four signals: clock line (I2S_CLK), serial data line

(I2S_SD), word select line (I2S_WS), and master system clock

(I2S_MCLK). FX3 can generate the system clock as an output

on I2S_MCLK or accept an external system clock input on

I2S_MCLK.

The sampling frequencies supported by the I

S interface are

8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz and 192 kHz.

Boot Options

FX3 can load boot images from various sources, selected by the

configuration of the PMODE pins. Following are the FX3 boot

options:

■ Boot from USB

■ Boot from I

■ Boot from SPI

❐ Cypress SPI Flash parts supported are

S25FS064S (64-Mbit), S25FS128S (128-Mbit) and

S25LFL064L (64-Mbit).

❐ W25Q32FW (32-Mbit) is also supported.

■ Boot from GPIF II ASync ADMux mode

■ Boot from GPIF II Sync ADMux mode

■ Boot from GPIF II ASync SRAM mode

Reset

Hard Reset

A hard reset is initiated by asserting the Reset# pin on FX3. The

specific reset sequence and timing requirements are detailed in

Figure 29 on page 43 and Table 23 on page 43. All I/Os are

tristated during a hard reset. Note however, that the on-chip

bootloader has control after a hard reset and it will configure I/O

signals depending on the selected boot mode; see AN76405 -

EZ-USB® FX3™ Boot Options for more details.

Soft Reset

In a soft reset, the processor sets the appropriate bits in the

PP_INIT control register. There are two types of Soft Reset:

■ CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset – This reset is identical to Hard Reset.

■ The firmware must be reloaded following a Whole Device

Reset.

Table 1. UART Interface Signals

Signal Description

TX Output signal

RX Input signal

CTS Flow control

RTS Flow control

Table 2. FX3 Booting Options

PMODE[2:0]

[1]

Boot From

F00 Sync ADMux (16-bit)

F01 Async ADMux (16-bit)

F11 USB boot

F0F Async SRAM (16-bit)

F1F I

C, On Failure, USB Boot is Enabled

1FF I

C only

0F1 SPI, On Failure, USB Boot is Enabled

Note

1. F indicates Floating.

CYUSB301X/CYUSB201X

Document Number: 001-52136 Rev. *X Page 10 of 58

Clocking

FX3 allows either a crystal to be connected between the XTALIN

and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins

can be left unconnected if they are not used.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

FX3 has an on-chip oscillator circuit that uses an external

19.2-MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal- or clock-frequency option. The

configuration options are shown in Table 3.

Clock inputs to FX3 must meet the phase noise and jitter require-

ments specified in Table 4.

The input clock frequency is independent of the clock and data

rate of the FX3 core or any of the device interfaces. The internal

PLL applies the appropriate clock multiply option depending on

the input frequency.

32-kHz Watchdog Timer Clock Input

FX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically wake up the FX3

in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock, which may be optionally supplied from

an external source on a dedicated FX3 pin.

The firmware can disable the watchdog timer. Requirements for the optional 32-kHz clock input are listed in Ta b le 5 .

Table 3. Crystal/Clock Frequency Selection

FSLC[2] FSLC[1] FSLC[0]

Crystal/Clock

Frequency

0 0 0 19.2-MHz crystal

1 0 0 19.2-MHz input CLK

1 0 1 26-MHz input CLK

1 1 0 38.4-MHz input CLK

1 1 1 52-MHz input CLK

Table 4. FX3 Input Clock Specifications

Parameter Description

Specification

Units

Min Max

Phase noise

100-Hz offset – –75

1-kHz offset – –104

10-kHz offset – –120

100-kHz offset – –128

1-MHz offset – –130

Maximum frequency deviation – – 150 ppm

Duty cycle – 30 70

%Overshoot – – 3

Undershoot – – –3

Rise time/fall time – – 3 ns

Table 5. 32-kHz Clock Input Requirements

Parameter Min Max Units

Duty cycle 40 60 %

Frequency deviation – ±200 ppm

Rise time/fall time – 200 ns

CYUSB301X/CYUSB201X

Document Number: 001-52136 Rev. *X Page 11 of 58

Power

FX3 has the following power supply domains:

■ IO_VDDQ: This is a group of independent supply domains for

digital I/Os. The voltage level on these supplies is 1.8 V to 3.3V.

FX3 provides six independent supply domains for digital I/Os

listed as follows (see Table 7 on page 15 for details on each of

the power domain signals):

❐ VIO1: GPIF II I/O

❐ VIO2: IO2

❐ VIO3: IO3

❐ VIO4: UART-/SPI/I

❐ VIO5: I

C and JTAG (supports 1.2 V to 3.3 V)

❐ CVDDQ: This is the supply voltage for clock and reset I/O. It

should be either 1.8 V or 3.3 V based on the voltage level of

the CLKIN signal.

❐ V

: This is the supply voltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-

tor, and other core analog circuits

• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-

ages for the USB 3.0 interface.

■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply

for the USB I/O and analog circuits. This supply powers the

USB transceiver through FX3’s internal voltage regulator.

VBATT is internally regulated to 3.3 V.

Note:

No specific power-up sequence for FX3 power domains.

Minimum power on reset time of 1 ms should be met and the

power domains must be stable for FX3 operation.

Power Modes

FX3 supports the following power modes:

■ Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

❐ Normal operating power consumption does not exceed the

sum of I

Core max and I

USB max (see Table 8 on page

19 for current consumption specifications).

❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be

turned off when the corresponding interface is not in use.

VIO1 cannot be turned off at any time if the GPIF II interface

is used in the application.

■ Low-power modes (see Table 6 ):

❐ Suspend mode with USB 3.0 PHY enabled (L1)

❐ Suspend mode with USB 3.0 PHY disabled (L2)

❐ Standby mode (L3)

❐ Core power-down mode (L4)

Table 6. Entry and Exit Methods for Low-Power Modes

Low-Power Mode Characteristics Methods of Entry Methods of Exit

Suspend Mode with

USB 3.0 PHY

Enabled (L1)

■ The power consumption in this mode does

not exceed ISB

■ USB 3.0 PHY is enabled and is in U3 mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block

alone is operational with its internal clock

while all other clocks are shut down

■ All I/Os maintain their previous state

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

■ The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■ All transactions must be completed before

FX3 enters Suspend mode (state of

outstanding transactions are not

preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

■ Firmware executing on

ARM926EJ-S core can put FX3 into

suspend mode. For example, on

USB suspend condition, firmware

may decide to put FX3 into suspend

mode

■ External Processor, through the use

of mailbox registers, can put FX3 into

suspend mode

■ D+ transitioning to low

or high

■ D- transitioning to low

or high

■ Impedance change on

OTG_ID pin

■ Resume condition on

SSRX±

■ Detection of VBUS

■ Level detect on

UART_CTS

(programmable

polarity)

■ GPIF II interface

assertion of CTL[0]

■ Assertion of RESET#

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