GN25L95: 2.5Gbps光纤模块，集成诊断监控与高速应用

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GN25L95是一款由Semtech公司提供的高性能光收发模块，专为10Gbps EPON、GPON FTTH ONT（Optical Network Unit）/ONT（Optical Network Terminal）以及BOSA-on-Board ONU（Bundled ONU with SFP Attachment）应用设计。这款模块的核心功能包括： 1. 高驱动能力：GN25L95支持高达100mA的偏置电流和90mA的调制电流输出，确保了在传输过程中的强大信号驱动能力。 2. 数字诊断监测(DDMI, Digital Diagnostic Monitoring Interface)：集成在芯片上的这项功能提供了实时的光模块状态监控，有助于快速识别并解决问题，提高系统的可靠性和维护效率。 3. 自动功率控制：自动平均功率控制和自动衰减比控制功能，能动态调整发送功率，保持最佳性能，同时减少功耗。 4. 快速的突发模式设置时间：优化的电路设计使得GN25L95在突发模式下的响应迅速，减少了信号延迟，提高了通信效率。 5. 当前DAC输出：用于APD（ avalanche photodiode,雪崩光电二极管）偏置控制，进一步提升了信号处理精度。 6. 安全特性：具备TX_SD和rogue ONU（非法ONU）报警功能，能够检测和防止潜在的安全威胁，保护网络稳定。 7. 功耗管理：支持电源降级和睡眠模式，有助于节能和延长模块寿命。 8. 接口兼容性：支持标准的SFF-8472接口规范，便于与各种标准光模块和设备无缝连接。 GN25L95作为一款光模块的核心组件，其设计目标是提供一个完整的解决方案，满足下一代光纤通信网络对高速、高效和智能化的需求。通过集成的数字诊断功能，可以简化系统调试，提升整体系统的性能和可靠性。无论是对于光接入网的标准化部署还是定制化应用，GN25L95都是一款值得信赖的选择。

GN25L95 16

Advanced Datasheet

Rev 1.0 – 28 January 2013

Proprietary & Confidential

Functional Block Diagram

STATE MACHINE

DDMI

CONTROLLER

NVM

DIGITAL

BURST

ENABLE

BIAS

DRIVER

DATA

INPUT

SAFETY LOGIC &

CONTROL

ADC &

TEMP

SENSOR

EEPROM

CONTROLLER

DIGITAL

INTERFACE

MOD

DRIVER

BEN-

BEN+

TXIN-

TXIN+ LASER+

LASER-

BIAS+

BIAS

MPD

_FAULT

TX_DISABLE/

TX_

SLEEP

SCL

SDA

Burst

Mean

Power

Monitor

CML

Limiter

LOS

Filter

Gain

RXOUT+

RXOUT-

RXIN+

RXIN-

LOS/SD

RSSI

_IN

TX_

VCC

_TX

VCC

_RX VCC_DIG

GND

APD

DAC

EE_SCL

_SDA

APD

DAC

RX_SLEEP

APC &

AUTO ER CONTROL

ADC_IN

Figure 9 – GN25L95 Functional Block Diagram

The GN25L95 is a pure CMOS combined burst-mode laser driver and limiting amplifier intended for

use in both burst-mode and continuous wave (CW), i.e. non-burst, telecom and datacom applications.

Both transmitter and receiver signal paths operate up to 2.5 Gbps making the GN25L95 suitable for

use in all popular module and protocol applications including BPON, EPON, GPON, OC-3, OC-12,

OC-48, GbE, and CSFP transceivers. The GN25L95 includes on-chip fully compliant SFF-8472 digital

diagnostics running on an internal state machine controller. The GN25L95 is particular suited to

BOSA-on-Board ONU applications that can take advantage of the on-chip APD DAC output. In

addition the GN25L95 has on-chip Non Volatile Memory (NVM) to store set-up data and is

programmed digitally via an I

C interface. The GN25L95 also includes on-chip sensors and analogue-

to-digital converters required for SFF-8472 DDMI monitoring of optical transceivers. The transmitter

contains full safety logic control circuitry to meet IEC-60825 eye safety requirements.

GN25L95 18

Advanced Datasheet

Rev 1.0 – 28 January 2013

Proprietary & Confidential

GN25L95 State Machine Controller

The GN25L95 features an internal state machine controller that runs all operating modes and

processes data internally to provide a digital diagnostic monitoring solution fully compliant to SFF-

8472 (when using external EEPROM). The state machine automatically detects what type of memory

is present and configures itself accordingly.

The GN25L95 has two I

C interfaces: (1) a main I

C (slave) interface for connection to an external

host master or external MCU and (2) an I

C (master) interface for connection to an external EEPROM

memory. The GN25L95 host interface responds to I

C addresses A0h and A2h by default as detailed

in the SFF-8472 multi-source agreement (MSA). The GN25L95 can also be set-up to respond to other

C addresses by changing the base address in the GN25L95 control settings – this can be

particularly useful for CSFP applications.

The GN25L95 implements a tabled approach to memory addressing to provide additional memory

locations for GN25L95 control settings and data that is accessed via the upper A2h addresses 80h to

FFh. The function of the upper A2h addresses is determined by the table select byte A2h 7Fh. The

user programs this byte to select which memory table to access at address A2h registers 80h to FFh.

The I

C slave interface physically reads and writes to internal volatile memory registers within the

GN25L95. Depending on the mode of operation, the state machine controller will load the internal

memory registers with data stored in internal NVM or external EEPROM on power-up.

The diagram below shows the full addressable memory space of the GN25L95.

0h Lower

SFF

-8472

h Upper

(SFF

-8079

)

h Lower

SFF-8472

Diagnostics

A2h Upper

SFF

-8472

User Writable

Memory Space

25L95

Control

Settings

MODULATION

LUT

BIAS

LUT

80h

FFh

00h

7Fh

FFh

Table Select =

0/1

Table Select =

2 Table Select = 4 Table Select

= 5 Table Select =

TabSel &

Passwd

7Ah

C Address

= A0h I

C Address =

A2h

Alm &

Wrn Set

F7h

GN25L

Factory

Settings

APD DAC

LUT

APCSET

LUT

A0h

C0h

Reserved

F7h

Figure 11 – GN25L95 Register Addressing

GN25L95 19

Advanced Datasheet

Rev 1.0 – 28 January 2013

Proprietary & Confidential

Modes of Operation

The GN25L95 is highly configurable and offers multiple set-up configurations to suit various

applications and operating conditions. In particular the modulation and bias currents can be

programmed over temperature using several methods of control: Direct programming of Modulation

and Bias DACs, Temperature indexed Look-Up Table (LUT) control of Modulation and Bias, Mean

Power control using the Automatic Power Control (APC) loop and Automatic Extinction Ratio control

– a closed loop control method for controlling modulation current over temperature.

There are three main modes of operation and configuration for memory interfacing on the GN25L95:

1. Internal NVM mode – uses internal NVM to store set-up data.

2. External EEPROM mode – uses external EEPROM to store set-up data.

3. External MCU mode – uses an external MCU to store and process data.

The GN25L95 automatically configures itself into 1 of the 3 operating modes during the power-up

process and dependent on the external connections made to the GN25L95. These are described

below in detail.

Internal NVM mode

The GN25L95 has enough on-chip non-volatile memory (NVM) to allow the GN25L95 to function

without the need for external EEPROM memory or control via an external MCU. The internal NVM

mode is particularly suited to low cost applications that do not require SFF-8472 compliance. In this

mode the SFF-8472 state machine controller is fully functional, however due to there being no

EEPROM memory the A0h and A2h memory areas are entirely volatile register space. The external

calibration is not used in this mode. The GN25L95 selects this mode of operation by default if an

external EEPROM is not found to be connected to the EE_SDA and EE_SCL I/O pins and those pins

are left unconnected. The GN25L95 then loads all setting and control data from the internal NVM.

h Lower

SFF-8472

0h Upper

(SFF-8079

)

A2h Lower

SFF

-8472

Diagnostics

A2h Upper

SFF

-8472

User Writable

Memory Space

25L95

Control

Settings

MODULATION

LUT

BIAS

LUT

00h

7Fh

80h

FFh

00h

7Fh

FFh

Table Select =

0/1

Table Select = 2

Table Select = 4 Table Select = 5

Table Select = 6

TabSel

& Passwd

7Ah

C Address = A0

h I

C Address = A2

Alm & Wrn Set

GN25L95

Factory

Settings

APD DAC

LUT

APCSET

LUT

Reserved

Figure 12 – GN25L95 NVM backed-up addresses

As shown in Figure 12 above, A0h and A2h (Table Select 0/1) are not stored in internal NVM and are

therefore completely volatile except for registers F7h to FFh which contain Alarm and Warning control

functions.

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