Nuvoton NCT6102D/NCT6106D：集成Super I/O监控关键硬件参数

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NCT6102D和NCT6106D是Nuvoton公司Super I/O产品系列中的成员，专为个人计算机硬件提供关键参数监控功能，包括电源电压、风扇转速和温度。这两款芯片集成了多种接口，以实现高效能和兼容性。 NCT6102D/NCT6106D数据手册发布于2012年1月11日，版本1.0，包含详细的规格和技术描述。以下是它们的主要特性和接口： 1. **通用描述**：该芯片集用于简化系统设计，通过集成多个接口，如LPC（Local Pulse Width Modulation）、FDC（Floppy Disk Controller）、多模式并行端口、串行接口（仅NCT6106D支持UART C-F）、键盘控制器(KBC)、CIR接口、硬件监控接口等，提供了全面的系统监控和管理功能。 2. **温度监控**：NCT6102D/NCT6106D采用电流模式来精确测量和报告设备温度，这对于维持系统稳定性至关重要。 3. **接口详细说明**： - **LPC接口**：提供了低速控制信号的连接，便于与主板上的其他部件通信。 - **FDC接口**：支持传统的软驱控制，现已逐渐过时，但仍然是某些旧系统设计的必要部分。 - **多模式并行端口**：兼容不同类型的并行设备连接。 - **串行接口**：用于串行通信，如调试和远程控制。 - **KBC接口**：键盘控制器，确保键盘输入的稳定传输。 - **CIR接口**：可能是某种特定的通信接口或电路接口。 - **硬件监控接口**：提供系统状态监控信息，如电源电压、风扇状态等。 - **Intel PECI接口**：用于处理器扩展通信接口，可能支持高级电源管理和节能特性。 - **配置与电源接口**：可能涉及到电源管理设置和配置选项。 - **高级睡眠状态控制**：支持节能和休眠模式的管理。 - **端口80消息显示**：可能用于显示特定的系统信息或提示。 - **SMBus接口**：一种低速总线接口，用于与外部设备通信，如传感器和外设。 - **电源引脚**：提供不同的电源电压选项。 - **AMD SB-TSI接口**：AMD特定的接口，可能与AMD平台集成。 - **DSW（Data Select Word）20**：可能用于数据选择或配置。 - **WatchDog定时器**：用于检测系统异常并恢复。 - **红外(IR)接口**：支持红外通信。 - **SUSPEND LED**：指示系统处于休眠状态。 - **通用目的I/O端口**：提供GPIO（通用输入/输出）以扩展外部设备连接。 - GPIO接口详细说明：每个GPIO接口可以单独配置为输入或输出，支持多种功能。这些芯片的强大之处在于它们的高度集成，能简化系统设计，提高效率，并且通过监测关键系统参数来保障系统的稳定运行。在选择和使用NCT6102D/NCT6106D时，开发者需要注意其具体版本的特性和兼容性，以便充分利用其提供的各种功能。

NCT6102D / NCT6106D

Publication Release Date: January 11, 2012

-XV- version: 1.0

25.10.1 GPIO Write Timing .................................................................................................................. 431

26. TOP MARKING SPECIFICATIONS .............................................................................................. ........... 432

27. ORDERING INFORMATION ......................................................................................................... ........... 433

28. PACKAGE SPECIFICATION ......................................................................................................... ........... 434

29. REVISION HISTORY .................................................................................................................... ........... 435

NCT6102D / NCT6106D 
 
                                                                                                   Publication Release Date: January 11, 2012 
-XVI-                                                                              version: 1.0 
LIST OF FIGURE 
Figure 3-1 NCT6102D / NCT6106D Block Diagram ............................................................................................ 5 
Figure 4-1 NCT6102D Pin Layout ....................................................................................................................... 6 
Figure 4-2 NCT6106D Pin Layout ....................................................................................................................... 7 
Figure 6-1 RSMRST# ........................................................................................................................................ 29 
Figure 6-2 PWROK ............................................................................................................................................ 29 
Figure 6-3 BKFD_CUT and LATCH_BKFD_CUT ............................................................................................. 31 
Figure 6-4 3VSBSW# ........................................................................................................................................ 32 
Figure 6-5 PSON# ............................................................................................................................................. 33 
Figure 6-6 PWROK Block Diagram ................................................................................................................... 34 
Figure 6-7 Illustration of Dual Color LED application ........................................................................................ 35 
Figure 6-8 Illustration of LED polarity ................................................................................................................ 37 
Figure 6-9 ASSC Application Diagram .............................................................................................................. 40 
Figure 7-1 Structure of the Configuration Register ............................................................................................ 46 
Figure 7-2 Configuration Register ..................................................................................................................... 48 
Figure 8-1 LPC Bus‟ Reads from / Write to Internal Registers .......................................................................... 51 
Figure 8-2 Serial Bus Write to Internal Address Register Followed by the Data Byte ...................................... 52 
Figure 8-3 Serial Bus Read from Internal Address Register ............................................................................. 52 
Figure 8-4 Analog Inputs and Application Circuit of the NCT6102D / NCT6106D ............................................ 53 
Figure 8-5 Monitoring Temperature from Thermistor ........................................................................................ 55 
Figure 8-6 Monitoring Temperature from Thermal Diode (Voltage Mode) ........................................................ 56 
Figure 8-7 Monitoring Temperature from Thermal Diode (Current Mode) ........................................................ 56 
Figure 8-8 PECI Temperature ........................................................................................................................... 58 
Figure 8-9 Temperature and Fan Speed Relation after Tbase Offsets ............................................................. 59 
Figure 8-10 Thermal Cruise
TM
 Mode Parameters Figure .................................................................................. 63 
Figure 8-11 Mechanism of Thermal Cruise
TM
 Mode (PWN Duty Cycle) ........................................................... 63 
Figure 8-12 Mechanism of Thermal Cruise
TM
 Mode (DC Output Voltage) ........................................................ 64 
Figure 8-13 Mechanism of Fan Speed Cruise
TM
 Mode ..................................................................................... 64 
Figure 8-14 SMART FAN
TM
 IV & Close Loop Fan Control Mechanism............................................................. 67 
Figure 8-15 Fan Control Duty Mode Programming Flow ................................................................................... 69 
Figure 8-16 Close-Loop Fan Control RPM Mode Programming Flow .............................................................. 70 
Figure 8-17 CPUFAN SMART FAN
TM
 IV Table Parameters Figure .................................................................. 71 
Figure 8-18 Fanout Step Relation of CPUFANOUT .......................................................................................... 71 
Figure 8-19 SYS TEMP and Weight Value Relations ....................................................................................... 72 
Figure 8-20 Weighting Duty Mode Programming Flow ..................................................................................... 73 
Figure 8-21 SMI Mode of Voltage and Fan Inputs ............................................................................................ 74 
Figure 8-22 Shut-down Interrupt Mode .............................................................................................................. 75 
Figure 8-23 SMI Mode of SYSTIN I ................................................................................................................... 76 
Figure 8-24 SMI Mode of SYSTIN II .................................................................................................................. 76 
Figure 8-25 Shut-down Interrupt Mode .............................................................................................................. 77 
Figure 8-26 SMI Mode of CPUTIN .................................................................................................................... 77 
Figure 8-27 OVT# Modes of Temperature Inputs ............................................................................................. 80 
Figure 8-28 Caseopen Mechanism ................................................................................................................... 81 
Figure 8-29 Power measurement architecture .................................................................................................. 81 

NCT6102D / NCT6106D

Publication Release Date: January 11, 2012

-XVII- version: 1.0

Figure 13-1 Keyboard and Mouse Interface .................................................................................................... 237

Figure 16-1 Power Control Mechanism ........................................................................................................... 258

Figure 16-2 Power Sequence from S5 to S0, then Back to S5 ....................................................................... 259

Figure 16-3 The previous state is “on” ............................................................................................................. 260

Figure 16-4 The previous state is “off”. ............................................................................................................ 260

Figure 16-5 Mechanism of Resume Reset Logic ............................................................................................ 262

Figure 17-1 Start Frame Timing with Source Sampled A Low Pulse on IRQ1 ................................................ 263

Figure 17-2 Stop Frame Timing with Host Using 17 SERIRQ Sampling Period ............................................. 265

Figure 20-1 Data Transfer Format ................................................................................................................... 273

Figure 20-2 SMBus Arbitration ........................................................................................................................ 274

Figure 20-3 Clock synchronization .................................................................................................................. 274

Figure 20-4 SMBus Master Block Diagram ..................................................................................................... 276

Figure 20-5 Programming Flow ....................................................................................................................... 277

Figure 20-6 TSI Routine .................................................................................................................................. 277

Figure 20-7 PCH Routine ................................................................................................................................ 278

Figure 20-8 PCH Routine ................................................................................................................................ 278

Figure 20-9 Manual Mode Programming Flow ................................................................................................ 279

Figure 21-1 Example of Fading LED ............................................................................................................... 289

Figure 22-1 PORT80 to UART Block Diagram ................................................................................................ 293

NCT6102D / NCT6106D 
 
                                                                                                   Publication Release Date: January 11, 2012 
-XVIII-                                                                              version: 1.0 
 
LIST OF TABLE 
Table 6-1 Pin Description .................................................................................................................................. 29 
Table 7-1 Devices of I/O Base Address ............................................................................................................ 47 
Table 8-1 Temperature Data Format ................................................................................................................. 55 
Table 8-2 Display Registers – at SMART FAN
TM
 I Mode .................................................................................. 64 
Table 8-3 Relative Registers – at Thermal Cruise
TM
 Mode ............................................................................... 65 
Table 8-4 Relative Registers – at Speed Cruise
TM
 Mode .................................................................................. 66 
Table 8-5 Relative Register-at SMART FAN
TM
 IV Control Mode ...................................................................... 67 
Table 8-6 Relative Register-at Weight Value Control ........................................................................................ 72 
Table 8-7 Relative Register of SMI functions .................................................................................................... 78 
Table 8-8 Relative Register of OVT functions ................................................................................................... 79 
Table 10-1 The Delays of the FIFO ................................................................................................................. 192 
Table 10-2  FDC Registers .............................................................................................................................. 202 
Table 11-1 Register Summary for UART ......................................................................................................... 213 
Table 12-1 Pin Descriptions for SPP, EPP, and ECP Modes ......................................................................... 225 
Table 12-2 EPP Register Addresses ............................................................................................................... 226 
Table 12-3 Address and Bit Map for SPP and EPP Modes ............................................................................ 226 
Table 12-4 ECP Mode Description .................................................................................................................. 230 
Table 12-5 ECP Register Addresses ............................................................................................................... 230 
Table 12-6 Bit Map of the ECP Registers ........................................................................................................ 230 
Table 13-1 Bit Map of Status Register ............................................................................................................. 238 
Table 13-2 KBC Command Sets ..................................................................................................................... 239 
Table 14-1 CIR Register Table ........................................................................................................................ 243 
Table 16-1 Bit Map of Logical Device A, CR[E4h], Bits[6:5] ............................................................................ 260 
Table 16-2 Definitions of Mouse Wake-Up Events .......................................................................................... 262 
Table 16-3 Timing and Voltage Parameters of RSMRST# ............................................................................. 262 
Table 17-1 SERIRQ Sampling Periods ........................................................................................................... 264 
Table 19-1 Relative Control Registers of GPIO 44, 45, 46 and 47 that Support Wake-Up Function .............. 267 
Table 19-2 GPIO Group Programming Table .................................................................................................. 267 
Table 19-3 GPIO Multi-Function Routing Table .............................................................................................. 271 
Table 19-4 GPIO Register Addresses ............................................................................................................. 272 
Table 20-1 SB-TSI Address Encoding ............................................................................................................. 275 
Table 20-2 PCH Command Summary ............................................................................................................. 275 
Table 20-3 SMBus Master Bank 0 Registers .................................................................................................. 280 
Table 21-1 Solid led configure mode ............................................................................................................... 291 
Table 21-2 Blink led configure mode ............................................................................................................... 291 
Table 21-3 Fading led configure mode ............................................................................................................ 291 

NCT6102D / NCT6106D

Publication Release Date: January 11, 2012

-1- Version: 1.0

1. GENERAL DESCRIPTION

The NCT6102D / NCT6106D is a member of Nuvoton‟s Super I/O product line. The NCT6102D / NCT6106D

monitors several critical parameters in PC hardware, including power supply voltages, fan speeds, and

temperatures. In terms of temperature monitoring, the NCT6102D / NCT6106D adopts the Current Mode (dual

current source) and thermistor sensor approach. The NCT6102D / NCT6106D also supports the Smart Fan control

system, including “SMART FAN

I and SMART FAN

IV, which makes the system more stable and user-friendly.

The NCT6102D / NCT6106D supports four – 360K, 720K, 1.2M, 1.44M, or 2.88M – disk drive types and data

transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s, 1 Mb/s, and 2 Mb/s. The disk drive adapter supports the functions of

floppy disk drive controller (compatible with the industry standard 82077/ 765), data separator, write pre-

compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt

and DMA logic. Such a wide range of functions integrated into one NCT6102D / NCT6106D greatly reduce the

number of required components to interface with floppy disk drives.

The NCT6102D supports 2 high-speed serial communication port (UART), and the NCT6106D supports 6 high-

speed serial communication port (UART). Each UART includes a 128-byte send/receive FIFO, a programmable

baud rate generator, complete modem-control capability, and a processor interrupt system. The UART supports

legacy speeds up to 115.2K bps as well as even higher baud rates of 230K, 460K, or 921K bps to support higher

speed modems.

The NCT6102D / NCT6106D supports the PC-compatible printer port (SPP), the bi-directional printer port (BPP),

the enhanced parallel port (EPP) and the extended capabilities port (ECP). The NCT6102D / NCT6106D supports

keyboard and mouse interface which is 8042-based keyboard controller.

The NCT6102D / NCT6106D provides flexible I/O control functions through a set of general purpose I/O (GPIO)

ports. These GPIO ports may serve as simple I/O ports or may be individually configured to provide alternative

functions.

The NCT6102D / NCT6106D supports the Intel

PECI (Platform Environment Control Interface), AMD

SB-TSI

interface, and Intel

Deep Sleep Well glue logic which helps customers to reduce the external circuits needed while

using Deep Sleep Well function.

The NCT6102D / NCT6106D supports to decode port 80 diagnostic messages on the LPC bus. This could help on

system power on debugging. It also supports two-color LED control to indicate system power states, Consumer IR

function for remote control purpose, and also Advanced Power Saving function to further reduce the power

consumption while the system is at S5 state.

The configuration registers inside the NCT6102D / NCT6106D support mode selection, function enable and disable,

and power-down selection. Furthermore, the configurable PnP features are compatible with the plug-and-play

feature in Windows, making the allocation of the system resources more efficient than ever.

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