Intel 82599 10GbE控制器详细规格与特性

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Intel 82599是一款高级的10GbE（千兆以太网）控制器，其详细的数据手册在2012年9月更新至版本2.76。该产品提供了两种配置选项：双端口10GbE设备（82599EN）或单端口10GbE设备，满足不同的网络应用需求。这款网卡的核心特性包括： 1. **硬件接口**：支持Serial Flash Interface（串行闪存接口）和4-wire SPI EEPROM Interface（四线式SPI电可擦除只读存储器接口），这使得用户可以方便地进行固件升级和定制化配置。 2. **LED控制**：提供了灵活的LED操作模式，允许软件或OEM进行定制，用于指示网络状态或诊断信息。 3. **保护存储**：具有受保护的EEPROM空间，用于存储私有配置数据，确保安全性。 4. **设备管理**：具备设备禁用功能，便于系统管理和维护。 5. **物理尺寸**：紧凑的25mm x 25mm封装，适合小型化设计。 6. **网络标准兼容性**：支持多种高速以太网标准，如10Gbps、1Gbps Ethernet、802.3ae的XAUI接口，以及1000BASE-BX和100BASE-TX标准，确保与不同环境的互通性。 7. **帧处理能力**：支持大帧（jumbo frames）处理，最高可达15.5KB，提升了数据传输效率。 8. **自动协商**：符合 Clause 73的自动协商机制，能自动识别并选择最优的工作模式。 9. **流量控制**：支持发送和接收PAUSE帧，以及接收FIFO阈值设置，有助于在网络拥塞时优化通信。 10. **统计与监控**：提供丰富的网络统计信息，便于管理和RMON（Remote Monitoring）功能，便于故障排查和性能优化。 11. **QoS和扩展功能**：支持802.1q VLAN（虚拟局域网），实现多租户网络架构；同时具备TCP/IP和UDP的接收校验和计算加速功能，提升数据包处理性能。 12. **协议支持**：具备IPv6支持，包括IP/TCP和IP/UDP的接收校验和计算，以及UDP分片检查和重组功能。 13. **中断管理**：采用了Message Signaled Interrupts (MSI)技术，提高中断处理效率，降低了CPU开销。 Intel 82599是一款功能强大且高度可定制的10GbE网卡，广泛应用于服务器、数据中心交换机和其他高性能网络设备中，能满足现代网络通信的高带宽、低延迟和智能管理的需求。

Intel

82599 10 GbE Controller—Contents

3.2.5 Transmit TCO Flow ...................................................................................................................... 116

3.2.5.1 Transmit Errors in Sequence Handling ............................................................................................ 117

3.2.5.2 TCO Command Aborted Flow......................................................................................................... 117

3.2.6 Concurrent SMBus Transactions..................................................................................................... 118

3.2.7 SMBus ARP Functionality .............................................................................................................. 118

3.2.7.1 SMBus ARP in Dual-/Single-Mode................................................................................................... 118

3.2.7.2 SMBus ARP Flow.......................................................................................................................... 119

3.2.7.2.1 SMBus ARP UDID Content .................................................................................................. 120

3.2.8 LAN Fail-Over Through SMBus....................................................................................................... 122

3.3 Network Controller — Sideband Interface (NC-SI).............................................................................................. 122

3.3.1 Electrical Characteristics............................................................................................................... 122

3.3.2 NC-SI Transactions...................................................................................................................... 123

3.4 EEPROM ....................................................................................................................................................... 123

3.4.1 General Overview ........................................................................................................................ 123

3.4.2 EEPROM Device........................................................................................................................... 123

3.4.3 EEPROM Vital Content .................................................................................................................. 123

3.4.4 Software Accesses....................................................................................................................... 124

3.4.5 Signature Field............................................................................................................................ 124

3.4.6 Protected EEPROM Space.............................................................................................................. 125

3.4.6.1 Initial EEPROM Programming......................................................................................................... 125

3.4.6.2 EEPROM Protected Areas .............................................................................................................. 125

3.4.6.3 Activating the Protection Mechanism .............................................................................................. 125

3.4.6.4 Non Permitted Access to Protected Areas in the EEPROM................................................................... 126

3.4.7 EEPROM Recovery ....................................................................................................................... 126

3.4.8 EEPROM Deadlock Avoidance ........................................................................................................ 127

3.4.9 VPD Support............................................................................................................................... 128

3.5 Flash ........................................................................................................................................................... 129

3.5.1 Flash Interface Operation ............................................................................................................. 129

3.5.2 Flash Write Control ...................................................................................................................... 130

3.5.3 Flash Erase Control...................................................................................................................... 130

3.5.4 Flash Access Contention ............................................................................................................... 130

3.6 Configurable I/O Pins — Software-Definable Pins (SDP) ...................................................................................... 131

3.7 Network Interface (MAUI Interface) ................................................................................................................. 135

3.7.1 10 GbE Interface ......................................................................................................................... 135

3.7.1.1 XAUI Operating Mode................................................................................................................... 136

3.7.1.1.1 XAUI Overview ................................................................................................................. 136

3.7.1.1.2 XAUI Operation................................................................................................................. 137

3.7.1.1.3 XAUI Electrical Characteristics ............................................................................................ 138

3.7.1.2 10GBASE-KX4 Operating Mode...................................................................................................... 138

3.7.1.2.1 KX4 Overview................................................................................................................... 138

3.7.1.2.2 KX4 Electrical Characteristics.............................................................................................. 139

3.7.1.3 10GBASE-KR Operating Mode........................................................................................................ 139

3.7.1.3.1 KR Overview .................................................................................................................... 140

3.7.1.3.2 KR Electrical Characteristics................................................................................................ 141

3.7.1.3.3 KR Reverse Polarity........................................................................................................... 141

3.7.1.4 10GBASE-CX4 Operating Mode...................................................................................................... 142

3.7.1.4.1 CX4 Overview................................................................................................................... 142

3.7.1.4.2 CX4 Electrical Characteristics.............................................................................................. 143

3.7.1.5 10GBASE-BX4 Operating Mode...................................................................................................... 143

3.7.1.5.1 10GBASE-BX4 Electrical Characteristics................................................................................

144

3.7.1.6 SFI Operating Mode ..................................................................................................................... 146

3.7.1.6.1 SFI Overview.................................................................................................................... 146

3.7.1.6.2 SFI Electrical Characteristics............................................................................................... 146

3.7.2 GbE Interface ............................................................................................................................. 147

3.7.2.1 1000BASE-KX Operating Mode ...................................................................................................... 147

3.7.2.1.1 KX Overview .................................................................................................................... 147

3.7.2.1.2 KX Electrical Characteristics................................................................................................ 148

3.7.2.2 1000BASE-BX Operating Mode ...................................................................................................... 149

3.7.2.2.1 BX Electrical Characteristics................................................................................................ 149

3.7.3 SGMII Support............................................................................................................................ 149

3.7.3.1 SGMII Overview .......................................................................................................................... 149

3.7.4 Auto Negotiation For Backplane Ethernet and Link Setup Features ..................................................... 150

3.7.4.1 Link Configuration ....................................................................................................................... 151

3.7.4.2 MAC Link Setup and Auto Negotiation............................................................................................. 151

3.7.4.3 Hardware Detection of Legacy Link Partner (Parallel Detection).......................................................... 152

3.7.4.4 MAUI Link Setup Flow .................................................................................................................. 152

3.7.4.5 Next Page Support ...................................................................................................................... 153

Contents—Intel

82599 10 GbE Controller

3.7.4.6 Forcing Link Up ........................................................................................................................... 153

3.7.4.7 Crossover................................................................................................................................... 154

3.7.5 Transceiver Module Support.......................................................................................................... 154

3.7.6 Management Data Input/Output (MDIO) Interface ........................................................................... 156

3.7.6.1 MDIO Timing Relationship to MDC.................................................................................................. 157

3.7.6.2 IEEE802.3 Clause 22 and Clause 45 Differences............................................................................... 158

3.7.6.3 MDIO Management Frame Structure .............................................................................................. 158

3.7.6.4 MDIO Direct Access ..................................................................................................................... 161

3.7.7 Ethernet Flow Control (FC)............................................................................................................ 161

3.7.7.1 MAC Control Frames and Reception of Flow Control Packets .............................................................. 162

3.7.7.1.1 MAC Control Frame — Other than FC ................................................................................... 162

3.7.7.1.2 Structure of 802.3X FC Packets........................................................................................... 162

3.7.7.1.3 PFC ................................................................................................................................. 163

3.7.7.1.4 Operation and Rules .......................................................................................................... 166

3.7.7.1.5 Timing Considerations........................................................................................................ 167

3.7.7.2 PAUSE and MAC Control Frames Forwarding.................................................................................... 167

3.7.7.3 Transmitting PAUSE Frames.......................................................................................................... 168

3.7.7.3.1 Priority Flow Control .......................................................................................................... 168

3.7.7.3.2 Operation and Rules .......................................................................................................... 168

3.7.7.3.3 Flow Control High Threshold — FCRTH ................................................................................. 168

3.7.7.3.4 Flow Control Low Threshold — FCRTL................................................................................... 170

3.7.7.3.5 Packet Buffer Size ............................................................................................................. 170

3.7.7.4 Link FC in DCB Mode.................................................................................................................... 171

3.7.8 Inter Packet Gap (IPG) Control and Pacing ...................................................................................... 171

3.7.9 MAC Speed Change at Different Power Modes..................................................................................172

4.0 Initialization ............................................................................................................................................... 175

4.1 Power Up...................................................................................................................................................... 175

4.1.1 Power-Up Sequence..................................................................................................................... 175

4.1.2 Power-Up Timing Diagram ............................................................................................................176

4.1.2.1 Timing Requirements ................................................................................................................... 177

4.1.2.2 Timing Guarantees ...................................................................................................................... 177

4.2 Reset Operation ............................................................................................................................................ 178

4.2.1 Reset Sources ............................................................................................................................. 178

4.2.1.1 LAN_PWR_GOOD......................................................................................................................... 178

4.2.1.2 PE_RST_N (PCIe Reset)................................................................................................................ 178

4.2.1.3 In-band PCIe Reset......................................................................................................................179

4.2.1.4 D3hot to D0 Transition ................................................................................................................. 179

4.2.1.5 Function Level Reset (FLR) Capability .............................................................................................179

4.2.1.5.1 FLR in Non-IOV Mode ........................................................................................................ 179

4.2.1.5.2 Physical Function FLR (PFLR) ..............................................................................................179

4.2.1.5.3 Virtual Function FLR (VFLR) ................................................................................................ 179

4.2.1.6 Software Resets .......................................................................................................................... 180

4.2.1.6.1 Software Reset ................................................................................................................. 180

4.2.1.6.2 Physical Function (PF) Software Reset.................................................................................. 180

4.2.1.6.3 VF Software Reset............................................................................................................. 181

4.2.1.6.4 Force TCO........................................................................................................................ 181

4.2.1.7 Link Reset .................................................................................................................................. 181

4.2.2 Reset in PCI-IOV Environment.......................................................................................................181

4.2.2.1 (RSTI)/(RSTD) ............................................................................................................................181

4.2.2.2 VF Receive Enable — PFVFRE / VF Transmit Enable — PFVFTE ........................................................... 182

4.2.3 Reset Effects............................................................................................................................... 182

4.3 Queue Disable............................................................................................................................................... 185

4.4 Function Disable............................................................................................................................................ 186

4.4.1 General...................................................................................................................................... 186

4.4.2 Overview.................................................................................................................................... 186

4.4.3 Control Options ........................................................................................................................... 188

4.4.4 Event Flow for Enable/Disable Functions ......................................................................................... 188

4.4.4.1 BIOS Disable the LAN Function at Boot Time by Using Strapping Option.............................................. 188

4.4.4.2 Multi-Function Advertisement ........................................................................................................ 189

4.4.4.3 Interrupt Utilization ..................................................................................................................... 189

4.4.4.4 Power Reporting.......................................................................................................................... 189

4.5 Device Disable .............................................................................................................................................. 189

4.5.1 Overview.................................................................................................................................... 189

4.5.2 BIOS Disable of the Device at Boot Time by Using the Strapping Option.............................................. 190

4.6 Software Initialization and Diagnostics.............................................................................................................. 190

4.6.1 Introduction................................................................................................................................ 190

4.6.2 Power-Up State........................................................................................................................... 190

Intel

82599 10 GbE Controller—Contents

4.6.3 Initialization Sequence ................................................................................................................. 191

4.6.3.1 Interrupts During Initialization ...................................................................................................... 191

4.6.3.2 Global Reset and General Configuration.......................................................................................... 191

4.6.4 100 Mb/s, 1 GbE, and 10 GbE Link Initialization............................................................................... 192

4.6.4.1 BX/ SGMII Link Setup Flow ........................................................................................................... 192

4.6.4.2 XAUI / BX4 / CX4 / SFI Link Setup Flow ......................................................................................... 192

4.6.4.3 KX / KX4 / KR Link Setup Flow Without Auto-Negotiation .................................................................. 192

4.6.4.4 KX / KX4 / KR Link Setup Flow With Auto-Negotiation ...................................................................... 193

4.6.5 Initialization of Statistics .............................................................................................................. 193

4.6.6 Interrupt Initialization .................................................................................................................. 193

4.6.7 Receive Initialization.................................................................................................................... 194

4.6.7.1 Dynamic Enabling and Disabling of Receive Queues.......................................................................... 196

4.6.7.1.1 Enabling .......................................................................................................................... 196

4.6.7.1.2 Disabling ......................................................................................................................... 196

4.6.7.1.3 Flushing the Packet Buffers............................................................................................ 196

4.6.7.2 RSC Enablement ......................................................................................................................... 197

4.6.7.2.1 Global Setting ................................................................................................................ 197

4.6.7.2.2 Per Queue Setting .......................................................................................................... 197

4.6.8 Transmit Initialization .................................................................................................................. 198

4.6.8.1 Dynamic Enabling and Disabling of Transmit Queues ........................................................................ 198

4.6.8.1.1 Enabling .......................................................................................................................... 198

4.6.8.1.2 Disabling ......................................................................................................................... 198

4.6.9 FCoE Initialization Flow ................................................................................................................ 199

4.6.10 Virtualization Initialization Flow ..................................................................................................... 200

4.6.10.1 VMDq Mode ................................................................................................................................ 200

4.6.10.1.1 Global Filtering and Offload Capabilities................................................................................ 200

4.6.10.1.2 Mirroring Rules ................................................................................................................. 200

4.6.10.1.3 Security Features.............................................................................................................. 200

4.6.10.1.4 Per Pool Settings............................................................................................................... 200

4.6.10.2 IOV Initialization ......................................................................................................................... 201

4.6.10.2.1 Physical Function (PF) Driver Initialization ............................................................................ 201

4.6.10.2.1.1 VF Specific Reset Coordination ................................................................................... 202

4.6.10.2.2 VF Driver Initialization ....................................................................................................... 202

4.6.10.2.3 Full Reset Coordination ...................................................................................................... 202

4.6.11 DCB Configuration ....................................................................................................................... 203

4.6.11.1 CPU Latency Considerations.......................................................................................................... 203

4.6.11.2 Link Speed Change Procedure ....................................................................................................... 203

4.6.11.3 Initial Configuration Flow.............................................................................................................. 203

4.6.11.3.1 General Case: DCB-on, VT-on............................................................................................. 204

4.6.11.3.2 DCB-On, VT-Off ................................................................................................................ 205

4.6.11.3.3 DCB-Off, VT-On ................................................................................................................ 205

4.6.11.3.4 DCB-Off, VT-Off ................................................................................................................ 206

4.6.11.4 Transmit Rate Scheduler .............................................................................................................. 207

4.6.11.5 Configuration Rules ..................................................................................................................... 208

4.6.11.5.1 TC Parameters.................................................................................................................. 208

4.6.11.5.2 VM Parameters ................................................................................................................. 211

4.6.12 Security Initialization ................................................................................................................... 213

4.6.12.1 Security Enablement Flow...............................................................................................

.............. 214

4.6.12.2 Security Disable Flow................................................................................................................... 214

4.6.13 Alternate MAC Address Support..................................................................................................... 215

5.0 Power Management and Delivery................................................................................................................ 217

5.1 Power Targets and Power Delivery ................................................................................................................... 217

5.2 Power Management ....................................................................................................................................... 217

5.2.1 Introduction to the 82599 Power States.......................................................................................... 217

5.2.2 Auxiliary Power Usage.................................................................................................................. 218

5.2.3 Power Limits by Certain Form Factors............................................................................................. 218

5.2.4 Interconnects Power Management ................................................................................................. 218

5.2.4.1 PCIe Link Power Management ....................................................................................................... 219

5.2.4.2 Network Interfaces Power Management .......................................................................................... 221

5.2.5 Power States .............................................................................................................................. 221

5.2.5.1 D0uninitialized State.................................................................................................................... 221

5.2.5.1.1 Entry to a D0u State ......................................................................................................... 222

5.2.5.2 D0active State ............................................................................................................................ 222

5.2.5.2.1 Entry to D0a State ............................................................................................................ 222

5.2.5.3 D3 State (PCI-PM D3hot).............................................................................................................. 222

5.2.5.3.1 Entry to D3 State.............................................................................................................. 223

5.2.5.3.2 Master Disable.................................................................................................................. 223

Contents—Intel

82599 10 GbE Controller

5.2.5.4 Dr State ..................................................................................................................................... 224

5.2.5.4.1 Dr Disable Mode................................................................................................................ 224

5.2.5.4.2 Entry to Dr State............................................................................................................... 225

5.2.6 Timing of Power-State Transitions.................................................................................................. 226

5.2.6.1 Transition From D0a To D3 and Back Without PE_RST_N .................................................................. 226

5.2.6.2 Transition From D0a To D3 And Back With PE_RST_N....................................................................... 227

5.2.6.3 Transition From D0a To Dr And Back Without Transition To D3 .......................................................... 228

5.2.6.4 Timing Requirements ................................................................................................................... 229

5.2.6.5 Timing Guarantees ...................................................................................................................... 229

5.3 Wake Up ...................................................................................................................................................... 230

5.3.1 Advanced Power Management Wake Up..........................................................................................230

5.3.2 ACPI Power Management Wake Up ................................................................................................ 230

5.3.3 Wake-Up Packets ........................................................................................................................ 231

5.3.3.1 Pre-Defined Filters....................................................................................................................... 231

5.3.3.1.1 Directed Exact Packet ........................................................................................................ 232

5.3.3.1.2 Directed Multicast Packet ................................................................................................... 232

5.3.3.1.3 Broadcast ........................................................................................................................ 232

5.3.3.1.4 Magic Packet .................................................................................................................... 233

5.3.3.1.5 ARP/IPv4 Request Packet ................................................................................................... 233

5.3.3.1.6 Directed IPv4 Packet ......................................................................................................... 234

5.3.3.1.7 Directed IPv6 Packet ......................................................................................................... 235

5.3.3.2 Flexible Filter .............................................................................................................................. 236

5.3.3.2.1 IPX Diagnostic Responder Request Packet ............................................................................ 236

5.3.3.2.2 Directed IPX Packet........................................................................................................... 237

5.3.3.2.3 IPv6 Neighbor Discovery Filter ............................................................................................237

5.3.4 Wake Up and Virtualization ...........................................................................................................238

6.0 Non-Volatile Memory Map ........................................................................................................................... 241

6.1 EEPROM General Map..................................................................................................................................... 241

6.2 EEPROM Software.......................................................................................................................................... 242

6.2.1 SW Compatibility Module — Word Address 0x10-0x14 ...................................................................... 242

6.2.2 PBA Number Module — Word Address 0x15-0x16............................................................................. 242

6.2.3 iSCSI Boot Configuration — Word Address 0x17 ..............................................................................243

6.2.4 VPD Module Pointer — Word Address 0x2F...................................................................................... 243

6.2.5 EEPROM PXE Module — Word Address 0x30-0x36 ............................................................................ 244

6.2.6 Alternate Ethernet MAC Address — Word Address 0x37 ....................................................................244

6.2.7 Checksum Word Calculation (Word 0x3F)........................................................................................ 245

6.2.8 Software Reserved Word 15 — Ext. Thermal Sensor Configuration Block Pointer — Word Address 0x26... 246

6.2.9 Software Reserved Word 16 — Alternate SAN MAC Block Pointer — Word Address 0x27 ........................ 246

6.2.9.1 Alternate SAN MAC Address Block.................................................................................................. 247

6.2.9.2 Capabilities - Offset 0x0 ........................................................................................................... 247

6.2.10 Software Reserved Word 17 — Active SAN MAC Block Pointer — Word Address 0x28 ............................ 248

6.2.10.1 Active SAN MAC Address Block ...................................................................................................... 248

6.3 EEPROM Hardware Sections ............................................................................................................................ 249

6.3.1 EEPROM Hardware Section — Auto-Load Sequence ..........................................................................249

6.3.2 EEPROM Init Module..................................................................................................................... 249

6.3.2.1 EEPROM Control Word 1 — Address 0x00........................................................................................ 249

6.3.2.2 EEPROM Control Word 2 — Address 0x01........................................................................................ 250

6.3.2.3 EEPROM Control Word 3 — Address 0x38........................................................................................ 250

6.3.3 PCIe Analog Configuration Module ................................................................................................. 251

6.3.3.1 Section Length — Offset 0x00 ....................................................................................................... 251

6.3.3.2 PCIe Analog Address — Offset 0x01, 0x03, 0x05... ..........................................................................252

6.3.3.3 PCIe Analog Data — Offset 0x02, 0x04, 0x06... ............................................................................... 252

6.3.4 Core 0/1 Analog Configuration Modules ..........................................................................................252

6.3.4.1 Section Length — Offset 0x00 ....................................................................................................... 252

6.3.4.2 Data and Address Words — Offset 0x01, 0x02, 0x03... .....................................................................253

6.3.5 PCIe General Configuration Module ................................................................................................ 253

6.3.5.1 Section Length — Offset 0x00 ....................................................................................................... 254

6.3.5.2 PCIe Init Configuration 1 — Offset 0x01 ......................................................................................... 254

6.3.5.3 PCIe Init Configuration 2 — Offset 0x02 ......................................................................................... 255

6.3.5.4 PCIe Init Configuration 3 — Offset 0x03 ......................................................................................... 255

6.3.5.5 PCIe Control 1 —Offset 0x04.............................................................................................

............ 256

6.3.5.6 PCIe Control 2 — Offset 0x05........................................................................................................ 256

6.3.5.7 PCIe LAN Power Consumption — Offset 0x06................................................................................... 257

6.3.5.8 PCIe Control 3 — Offset 0x07........................................................................................................ 257

6.3.5.9 PCIe Sub-System ID — Offset 0x08 ............................................................................................... 258

6.3.5.10 PCIe Sub-System Vendor ID — Offset 0x09..................................................................................... 259

6.3.5.11 PCIe Dummy Device ID — Offset 0x0A ...........................................................................................259

Intel

82599 10 GbE Controller—Contents

6.3.5.12 PCIe Device Revision ID —Offset 0x0B ........................................................................................... 259

6.3.5.13 IOV Control Word 1 — Offset 0x0C ................................................................................................ 259

6.3.5.14 IOV Control Word 2 — Offset 0x0D ................................................................................................ 260

6.3.5.15 Serial Number Ethernet MAC Address — Offset 0x11 ........................................................................ 260

6.3.5.16 Serial Number Ethernet MAC Address — Offset 0x12 ........................................................................ 261

6.3.5.17 Serial Number Ethernet MAC Address — Offset 0x13 ........................................................................ 261

6.3.5.18 PCIe L1 Exit latencies — Offset 0x14.............................................................................................. 261

6.3.5.19 Reserved — Offset 0x15 ............................................................................................................... 262

6.3.6 PCIe Configuration Space 0/1 Modules ........................................................................................... 262

6.3.6.1 Section Length — Offset 0x00 ....................................................................................................... 262

6.3.6.2 Control Word — Offset 0x01 ......................................................................................................... 263

6.3.6.3 Device ID — Offset 0x02 Device ID................................................................................................ 263

6.3.6.4 CDQM Memory Base 0/1 Low — Offset 0x03 [Reserved] ................................................................... 264

6.3.6.5 CDQM Memory Base 0/1 High — Offset 0x04 [Reserved] .................................................................. 264

6.3.6.6 EEPROM PCIe Configuration Space 0/1 - Offset 0x05 [Reserved]........................................................ 264

6.3.7 LAN Core 0/1 Modules.................................................................................................................. 264

6.3.7.1 Section Length — Offset 0x00 ....................................................................................................... 265

6.3.7.2 Ethernet MAC Address Registers.................................................................................................... 265

6.3.7.2.1 Ethernet MAC Address Register1 — Offset 0x01 .................................................................... 265

6.3.7.2.2 Ethernet MAC Address Register2 — Offset 0x02 .................................................................... 265

6.3.7.2.3 Ethernet MAC Address Register3 — Offset 0x03 .................................................................... 266

6.3.7.3 LED Configuration........................................................................................................................ 266

6.3.7.3.1 LED Control Lower Word — Offset 0x04 ............................................................................... 266

6.3.7.3.2 LED control Upper Word — Offset 0x05 ................................................................................ 266

6.3.7.4 SDP Control — Offset 0x06 ........................................................................................................... 266

6.3.7.5 Filter Control — Offset 0x07.......................................................................................................... 267

6.3.8 MAC 0/1 Modules ........................................................................................................................ 267

6.3.8.1 Section Length — Offset 0x00 ....................................................................................................... 268

6.3.8.2 Link Mode Configuration – Offset 0x01 ........................................................................................... 268

6.3.8.3 SWAP Configuration — Offset 0x02 ................................................................................................ 269

6.3.8.4 Swizzle and Polarity Configuration — Offset 3.................................................................................. 270

6.3.8.5 Auto Negotiation Defaults — Offset 4 ............................................................................................. 270

6.3.8.6 AUTOC2 Upper Half – Offset 5....................................................................................................... 272

6.3.8.7 SGMIIC Lower Half — Offset 6....................................................................................................... 272

6.3.8.8 KR-PCS configurations — Offset 7.................................................................................................. 273

6.3.9 CSR 0/1 Auto Configuration Modules .............................................................................................. 273

6.3.9.1 Section Length — Offset 0x0......................................................................................................... 274

6.3.9.2 CSR Address — Offset 0x1, 0x4, 0x7.............................................................................................. 274

6.3.9.3 CSR Data LSB — Offset 0x2, 0x5, 0x8............................................................................................ 274

6.3.9.4 CSR Data MSB — Offset 0x3, 0x6, 0x9... ........................................................................................ 274

6.4 Firmware Module........................................................................................................................................... 275

6.4.1 Test Configuration Module ............................................................................................................ 275

6.4.1.1 Section Header — Offset 0x0 ........................................................................................................ 275

6.4.1.2 SMBus Address — Offset 0x1 ........................................................................................................ 275

6.4.1.3 Loopback Test Configuration — Offset 0x2 ...................................................................................... 276

6.4.2 Common Firmware Parameters — (Global MNG Offset 0x3) ............................................................... 276

6.4.3 Pass Through LAN 0/1 Configuration Modules .................................................................................. 277

6.4.3.1 Section Header — Offset 0x0 ........................................................................................................ 277

6.4.3.2 LAN 0/1 IPv4 Address 0 (LSB) MIPAF0 — Offset 0x01....................................................................... 277

6.4.3.3 LAN 0/1 IPv4 Address 0 (MSB) (MIPAF0) — Offset 0x02 ................................................................... 277

6.4.3.4 LAN 0/1 IPv4 Address 1 MIPAF1 — Offset 0x03:0x04 ....................................................................... 278

6.4.3.5 LAN 0/1 IPv4 Address 2 MIPAF2 — Offset 0x05:0x06 ....................................................................... 278

6.4.3.6 LAN 0/1 IPv4 Address 3 MIPAF3 — Offset 0x07:0x08 ....................................................................... 278

6.4.3.7 LAN 0/1 Ethernet MAC Address 0 (LSB) MMAL0 — Offset 0x09 .......................................................... 278

6.4.3.8 LAN 0/1 Ethernet MAC Address 0 (Mid) MMAL0 — Offset 0x0A........................................................... 278

6.4.3.9 LAN 0/1 Ethernet MAC Address 0 (MSB) MMAH0 — Offset 0x0B ......................................................... 279

6.4.3.10 LAN 0/1 Ethernet MAC Address 1 MMAL/H1 — Offset 0x0C:0x0E........................................................ 279

6.4.3.11 LAN 0/1 Ethernet MAC Address 2 MMAL/H2 — Offset 0x0F:0x11 ........................................................ 279

6.4.3.12 LAN 0/1 Ethernet MAC Address 3 MMAL/H3 — Offset 0x12:0x14........................................................ 279

6.4.3.13 LAN 0/1 UDP Flexible Filter Ports 0:15 (MFUTP Registers) - Offset 0x15:0x24 ...................................... 279

6.4.3.14 LAN 0/1 VLAN Filter 0 — 7 (MAVTV Registers) - Offset 0x25:0x2C ..................................................... 280

6.4.3.15 LAN 0/1 Manageability Filters Valid (MFVAL LSB) — Offset 0x2D ........................................................ 281

6.4.3.16 LAN 0/1 Manageability Filters Valid (MFVAL MSB) — Offset 0x2E........................................................ 281

6.4.3.17 LAN 0/1 MANC value LSB (LMANC LSB) — Offset 0x2F ..................................................................... 282

6.4.3.18 LAN 0/1 MANC Value MSB (LMANC MSB) — Offset 0x30.................................................................... 282

6.4.3.19 LAN 0/1 Receive Enable 1 (LRXEN1) — Offset 0x31.......................................................................... 282

6.4.3.20 LAN 0/1 Receive Enable 2 (LRXEN2) — Offset 0x32.......................................................................... 283

剩余1055页未读，继续阅读

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