1.2 TSV-Based 3-D IC Design Challenges 3
The IC industry has enthusiastically embraced 3-D stacking technology, and
progress is being made to advance design methodologies, tools, and core tech-
nologies. Qualcomm Inc., the biggest near-term consumer of 3-D ICs for mobile
devices, is working on standardizing the process flow [39]. All major EDA vendors
are developing design tools to support each stage of the 3-D IC design cycle.
MIT Lincoln Labs has introduced a fully depleted silicon-on-insulator (FDSOI)
process that can stack three dies using wafer–wafer oxide bonding [2]. Tezzaron
Inc. has demonstrated a variety of 3-D ICs (memory, FPGA, and mixed signal) using
a 180 nm technology node and wafer-level, via-first, and metal-to-metal thermal
bonding [84]. Foundries are working in close relation with research organizations to
develop fabrication processes that meet 3-D stacking requirements [27, 51, 86,96].
1.2 TSV-Based 3-D IC Design Challenges
TSVs offer higher interconnect density and better performance than wire-bond
stacking technology [10]. However, fabricating vertical interconnects that pass
through dies containing substrate, devices, and interconnect, poses manufacturing
and performance challenges. A few of these challenges are discussed in this section.
TSVs occupy valuable silicon real estate. As a point of reference, ITRS predicts
the minimum TSV area to realize global-level inter-die connections to be 16 μm
2
[5], whereas the area of a 6T SRAM cell for 45 nm Hi-K Metal-Gate technology is
0.346μm
2
[19]. TSVs thus create blockages (≈ 46× the SRAM cell area): neither
a device can be fabricated nor a signal can be routed through the area occupied by a
TSV. TSVs therefore impact device density, die floor-plan, and interconnect routing.
Manufacturing constraints associated with TSV etch and via filling processes
dictate TSV size [38]. Smaller TSV sizes are desirable but require the silicon (Si)
substrate to be thinned to a thickness of 100 to 10 μm, or even less in bulk CMOS
technology [76]. To fabricate a TSV of size 5 μm assuming a practical aspect ratio of
10:1, the maximum die thickness will be 50 μm. Technical innovations are needed
to manufacture and bond thin wafers [86].
A TSV is a metallic, usually copper (Cu), interconnect extending through the
substrate and insulated by a dielectric material. Any signal transitions through a
TSV create noise within abutting substrate. This TSV-induced substrate noise poses
a major threat to the performance of neighboring devices and neighboring TSVs.
TSV-induced substrate noise increases leakage current, which increases static power
consumption and can turn transistors in the “off” state to the “on” state and vice
versa [91].
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