3D集成电路设计：TSV工艺详解

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《Designing TSVs for 3D Integrated Circuits》是由Nauman Khan和Soha Hassoun合著的一本SpringerBriefs系列书籍，专注于3D集成电路设计中的Through Silicon Vias（TSV）技术。TSV是一种创新的连接技术，它允许在三维空间内将多层芯片堆叠在一起，从而极大地增强了集成电路的性能和密度，对于现代电子系统的设计和制造具有重要意义。这本书的内容深入探讨了TSV在3D集成电路设计中的应用和挑战，包括但不限于以下几个方面： 1. **TSV的基本原理**：章节中详细解释了TSV的工作原理，如何通过在硅片内部创建贯穿性的通孔来实现不同层之间的电气连接，以及这种连接方式相较于传统二维连接方式的优势，如减小信号延迟、增加封装密度等。 2. **设计流程与方法**：书中介绍了设计3D集成电路时采用的TSV布局、布线、模拟仿真以及优化策略，涵盖了从概念到实际实施的关键步骤和技术。 3. **材料科学与制造技术**：讨论了用于制造TSV的不同材料选择，如硅、硅氮化物等，并强调了工艺控制对TSV性能和可靠性的影响。 4. **可靠性与测试**：针对TSV可能带来的挑战，如热应力、互连可靠性等问题，书中会涉及相应的测试方法和可靠性评估。 5. **案例研究与应用示例**：书中可能包含实际的3D IC设计案例，展示TSV在处理器、存储器、通信和信号处理等领域的应用实例，帮助读者理解技术在实际产品中的价值。 6. **未来趋势和发展**：最后，作者可能会对未来3D集成电路设计中TSV技术的发展方向和潜在的研究热点进行预测，如新型TSV结构、高性能封装解决方案等。《Designing TSVs for 3D Integrated Circuits》是一本深入浅出的技术指南，不仅适合从事IC设计的专业人士，也对对3D电子封装技术感兴趣的研究生和工程师具有很高的参考价值。通过阅读此书，读者能够掌握3D集成电路设计中利用TSV技术的关键知识和实践技巧，推动电子器件性能的进一步提升。

1.2 TSV-Based 3-D IC Design Challenges 3

The IC industry has enthusiastically embraced 3-D stacking technology, and

progress is being made to advance design methodologies, tools, and core tech-

nologies. Qualcomm Inc., the biggest near-term consumer of 3-D ICs for mobile

devices, is working on standardizing the process ﬂow [39]. All major EDA vendors

are developing design tools to support each stage of the 3-D IC design cycle.

MIT Lincoln Labs has introduced a fully depleted silicon-on-insulator (FDSOI)

process that can stack three dies using wafer–wafer oxide bonding [2]. Tezzaron

Inc. has demonstrated a variety of 3-D ICs (memory, FPGA, and mixed signal) using

a 180 nm technology node and wafer-level, via-ﬁrst, and metal-to-metal thermal

bonding [84]. Foundries are working in close relation with research organizations to

develop fabrication processes that meet 3-D stacking requirements [27, 51, 86,96].

1.2 TSV-Based 3-D IC Design Challenges

TSVs offer higher interconnect density and better performance than wire-bond

stacking technology [10]. However, fabricating vertical interconnects that pass

through dies containing substrate, devices, and interconnect, poses manufacturing

and performance challenges. A few of these challenges are discussed in this section.

TSVs occupy valuable silicon real estate. As a point of reference, ITRS predicts

the minimum TSV area to realize global-level inter-die connections to be 16 μm

[5], whereas the area of a 6T SRAM cell for 45 nm Hi-K Metal-Gate technology is

0.346μm

[19]. TSVs thus create blockages (≈ 46× the SRAM cell area): neither

a device can be fabricated nor a signal can be routed through the area occupied by a

TSV. TSVs therefore impact device density, die ﬂoor-plan, and interconnect routing.

Manufacturing constraints associated with TSV etch and via ﬁlling processes

dictate TSV size [38]. Smaller TSV sizes are desirable but require the silicon (Si)

substrate to be thinned to a thickness of 100 to 10 μm, or even less in bulk CMOS

technology [76]. To fabricate a TSV of size 5 μm assuming a practical aspect ratio of

10:1, the maximum die thickness will be 50 μm. Technical innovations are needed

to manufacture and bond thin wafers [86].

A TSV is a metallic, usually copper (Cu), interconnect extending through the

substrate and insulated by a dielectric material. Any signal transitions through a

TSV create noise within abutting substrate. This TSV-induced substrate noise poses

a major threat to the performance of neighboring devices and neighboring TSVs.

TSV-induced substrate noise increases leakage current, which increases static power

consumption and can turn transistors in the “off” state to the “on” state and vice

versa [91].

4 1 Introduction

The large mismatch between the coefﬁcients of thermal expansion (CTE) of

metallic TSV (17.5E−6/

◦

C for Cu) and Si substrate (2.5 E−6/

◦

C) results in serious

reliability concerns [94, 115]. High temperature loadings during fabrication create

thermal stress in the substrate, which in turn impacts the mobility of carriers and

affects device performance [95].

Power delivery design for 3-D ICs is a challenging task due to increased device

density and package asymmetry [46,117]. While the die closest to the package can

get power supply directly from the package, TSVs are required to deliver power

to the dies further away from the package. TSV size and placement are design

decisions. Technology and design choices must be explored to minimize TSV area

penalty and meet power requirements.

Thermal management is one of the biggest problems faced by 3-D IC design.

TSVs can be used to extract heat from the dies away from the heat sink [117].

Optimizing the number and placement of TSVs to meet the thermal budget requires

accurate modeling and novel algorithmic and design approaches [120].

1.3 Contributions

The work proposed in this book is original and innovative as it is one of the ﬁrst to

explore design issues concerning TSVs in 3-D ICs. The key contributions are:

• Characterizing the impact of TSVs on substrate noise using a simple circuit

model and a three-dimensional ﬁnite element solver.

• Proposing an effective technique, the GND plug, to mitigate TSV-induced

substrate noise, and comparing the performance and area penalty of the GND

plug with other noise mitigation techniques including thicker dielectric liner and

backside ground plane.

• Performing the ﬁrst comparative study of system-level power delivery for

2-D and 3-D ICs utilizing realistic workloads, and investigating methods for

achieving 2-D-like power quality in 3-D ICs.

• Studying the use of coaxial TSVs for power delivery and assessing the beneﬁts in

terms of the number of routing blockages, decoupling capacitance, and sharing

of signal and power routing.

• Investigating algorithmic solutions to estimate early in the design cycle the

number of TSVs required for power delivery network design.

• Exploring using carbon nanotubes (CNTs), as an alternative to Cu, for on-chip

power delivery and assessing their performance.

The contributions proposed herein pave the way for 3-D IC design using TSVs

and motivate further research into this emerging technology.

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