Intel SSE4编程参考手册（2007年版）

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本资源是关于Intel SSE4编程参考文档（Reference Number: D91561-001），发布日期为2007年4月。Intel SSE4是第4代Streaming SIMD Extensions（单指令多数据）架构的一部分，旨在增强处理器的并行计算能力，特别在处理大量浮点运算和向量操作时提供显著性能提升。SSE4.1和SSE4.2是其两个主要版本，它们引入了新的指令集，如AES-NI（高级加密标准新指令集）用于加速密码学运算，PCLMULQDQ（乘法和移位）提高了整数运算效率，以及对矩阵乘法的支持。文档强调了几个关键点： 1. Intel SSE4编程指南：提供了详细的编程接口和指令集描述，开发人员需根据这些信息设计高效的代码，充分利用SSE4的功能。 2. 法律责任声明：文档明确指出，除非按照Intel的产品销售条款，否则不授予任何知识产权许可。同时，Intel不对产品的销售或使用承担任何明示或默示的保修责任，包括但不限于特定用途适用性、产品质量或对专利、版权和其他知识产权的侵犯。 3. 预留和未定义特性：开发人员不应依赖于文档中标记为“预留”或“未定义”的功能，因为这些可能会在未来更改，不保证稳定性。错误地使用这些特性可能导致开发者软件在Intel处理器上运行时出现不可预测的行为或失败。 SSE4.1和SSE4.2的引入，使得现代处理器能够执行更复杂的数学和数据处理任务，对于科学计算、图形渲染、音频处理等领域有着显著影响。学习和熟练运用SSE4指令集对于编写高性能的多线程程序至关重要。然而，开发人员必须时刻关注Intel的官方更新和文档，确保他们的代码与当前架构兼容，并避免潜在的兼容性问题。这本PDF文档不仅提供了深入的编程指南，还明确了使用Intel SSE4技术的注意事项和限制，是软件开发者在利用SSE4进行并行编程时的重要参考资料。

SSE4 FEATURES

The other SSE4.1 instructions with floating-point arguments (BLENDPS, BLENDPD,

BLENDVPS, BLENDVPD, INSERTPS, EXTRACTPS) do not signal any SIMD numeric

exceptions.

2.3 SSE4.2 INSTRUCTION SET

Five of the seven SSE4.2 instructions can use an XMM register as a source or desti-

nation. These include four text/string processing instructions and one packed quad-

word compare SIMD instruction. Programming these five SSE4.2 instructions is

similar to programming 128-bit Integer SIMD in SSE2/SSSE3. SSE4.2 does not

provide any 64-bit integer SIMD instructions.

The remaining two SSE4.2 instructions uses general-purpose registers to perform

accelerated processing functions in specific application areas.

2.3.1 String and Text Processing Instructions

String and text processing instructions in SSE4.2 allocates 4 opcodes to provide a

rich set of string and text processing capabilities that traditionally required many

more opcodes. These 4 instructions use XMM registers to process string or text

elements of up to 128-bits (16 bytes or 8 words). Each instruction uses an immediate

byte to support a rich set of programmable controls. A string-processing SSE4.2

instruction returns the result of processing each pair of string elements using either

an index or a mask.

The capabilities of the string/text processing instructions include:

• Handling string/text fragments consisting of bytes or words, either signed or

unsigned

Table 2-7. SIMD numeric exceptions signaled by SSE4.1

DPPS DPPD ROUNDPS

ROUNDSS

ROUNDPD

ROUNDSD

Overflow X X

Underflow X X

InvalidXXX

(1)

Inexact PrecisionXXX

(2)

Denormal X X

NOTE:

1. Invalid is signaled only if Src = SNaN.

2. Precision is ignored (regardless of the MXCSR precision mask) if if imm8[3] = ‘1’.

SSE4 FEATURES

• Support for partial string or fragments less than 16 bytes in length, using either

explicit length or implicit null-termination

• Four types of string compare operations on word/byte elements

• Up to 256 compare operations performed in a single instruction on all string/text

element pairs

• Built-in aggregation of intermediate results from comparisons

• Programmable control of processing on intermediate results

• Programmable control of output formats in terms of an index or mask

• Bi-directional support for the index format

• Support for two mask formats: bit or natural element width

• Not requiring 16-byte alignment for memory operand

The four SSE4.2 instructions that process text/string fragments are:

• PCMPESTRI — Packed compare explict-length strings, return index in ECX/RCX

• PCMPESTRM — Packed compare explict-length strings, return mask in XMM0

• PCMPISTRI — Packed compare implict-length strings, return index in ECX/RCX

• PCMPISTRM — Packed compare implict-length strings, return mask in XMM0

All four require the use of an immediate byte to control operation. The two source

operands can be XMM registers or a combination of XMM register and memory

address. The immediate byte provides programmable control with the following

attributes:

• Input data format

• Compare operation mode

• Intermediate result processing

• Output selection

Depending on the output format associated with the instruction, the text/string

processing instructions implicitly uses either a general-purpose register (ECX/RCX)

or an XMM register (XMM0) to return the final result.

Two of the four text-string processing instructions specify string length explicitly.

They use two general-purpose registers (EDX, EAX) to specify the number of valid

data elements (either word or byte) in the source operands. The other two instruc-

tions specify valid string elements using null termination. A data element is consid-

ered valid only if it has a lower index than the least significant null data element.

2.3.1.1 Memory Operand Alignment

The text and string processing instructions in SSE4.2 do not perform alignment

checking on memory operands. This is different from most other 128-bit SIMD

instructions accessing the XMM registers. The absence of an alignment check for

APPLICATION PROGRAMMING MODEL

CHAPTER 3

APPLICATION PROGRAMMING MODEL

The application programming environment for SSE4 is similar to that of Streaming

SIMD Extensions (SSE), SSE2, SSE3, and SSSE3.

3.1 CPUID

The CPUID instruction is extended to provide additional information, including three

feature flags that indicate support for SSE4 instructions. CPUID’s output is depen-

dent on the contents of the EAX register upon execution. For example, the following

pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return

Value and the Vendor Identification String in the appropriate registers:

MOV EAX, 00H

CPUID

Table 3-1 shows information returned, depending on the initial value loaded into the

EAX register. Table 3-2 shows the maximum CPUID input value recognized for each

family of Intel 64 and IA-32 processors on which CPUID is implemented.

Two types of information are returned: basic and extended function information. If a

value is entered for CPUID.EAX is invalid for a particular processor, the data for the

highest basic information leaf is returned. For example, using the Intel

Core™2 Duo

processor, the following is true:

CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)

CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)

CPUID.EAX = 0BH (* INVALID: Returns the same information as CPUID.EAX = 0AH. *)

CPUID.EAX = 80000008H (* Returns virtual/physical address size data. *)

CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0AH. *)

CPUID can be executed at any privilege level to serialize instruction execution. Seri-

alizing instruction execution guarantees that any modifications to flags, registers,

and memory for previous instructions are completed before the next instruction is

fetched and executed.

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